36 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \  argument
38 	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \  argument
42 	 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
43 	 WREG32(reg, value))
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \  argument
47 	 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
48 	 RREG32(reg))
50 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
51 	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
53 					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
55 				~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
59 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,  …
61 					adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
66 #define RREG32_SOC15(ip, inst, reg) \  argument
67 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)  argument
72 #define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HW…  argument
74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
75 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
78 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
79 	 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
82 #define WREG32_SOC15(ip, inst, reg, value) \  argument
83 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
86 #define WREG32_SOC15_IP(ip, reg, value) \  argument
87 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
89 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \  argument
90 	 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
93 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
96 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
97 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask)      \  argument
102 	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
103 	#reg, expected_value, mask)
105 #define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask)  \  argument
107 	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
108 	#reg, expected_value, mask)
110 #define WREG32_RLC(reg, value) \  argument
111 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
113 #define WREG32_RLC_EX(prefix, reg, value, inst) \  argument
122 			WREG32(r1, (reg | 0x80000000));	\
131 				pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);	\
133 			WREG32(reg, value); \
138 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
139 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
142 #define RREG32_RLC(reg) \  argument
143 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \  argument
146 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
148 #define RREG32_RLC_NO_KIQ(reg, hwip) \  argument
149 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
151 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
153 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
169 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
170 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
174 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
178 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
180 			uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\
184 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
185 	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
186 			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
188 			      ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
191 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
192 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AM…
194 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
195 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…
198 #define RREG32_SOC15_EXT(ip, inst, reg, ext) \  argument
199 	RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
202 #define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \  argument
203 	WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \