Lines Matching +full:2 +full:x
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
79 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
82 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
90 #define SPLL_REF_DIV(x) ((x) << 4) argument
92 #define SPLL_PDIV_A(x) ((x) << 20) argument
96 #define SCLK_MUX_SEL(x) ((x) << 0) argument
101 #define SPLL_FB_DIV(x) ((x) << 0) argument
111 # define SPLL_REFCLK_SEL(x) ((x) << 26) argument
116 #define CLK_S(x) ((x) << 4) argument
120 #define CLK_V(x) ((x) << 0) argument
138 # define UPLL_PDIV_A(x) ((x) << 0) argument
140 # define UPLL_PDIV_B(x) ((x) << 8) argument
142 # define VCLK_SRC_SEL(x) ((x) << 20) argument
144 # define DCLK_SRC_SEL(x) ((x) << 25) argument
147 # define UPLL_FB_DIV(x) ((x) << 0) argument
157 # define MPLL_CLKOUT_SEL(x) ((x) << 8) argument
162 # define BCLK_AS_XCLK (1 << 2)
168 # define CMON_CLK_SEL(x) ((x) << 0) argument
170 # define TMON_CLK_SEL(x) ((x) << 8) argument
173 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) argument
175 # define ZCLK_SEL(x) ((x) << 8) argument
179 #define DPM_EVENT_SRC(x) ((x) << 0) argument
181 #define DIG_THERM_DPM(x) ((x) << 14) argument
185 #define FDO_PWM_DUTY(x) ((x) << 9) argument
189 #define DIG_THERM_INTH(x) ((x) << 8) argument
192 #define DIG_THERM_INTL(x) ((x) << 16) argument
199 #define TEMP_SEL(x) ((x) << 20) argument
203 #define ASIC_MAX_TEMP(x) ((x) << 0) argument
206 #define CTF_TEMP(x) ((x) << 9) argument
211 #define FDO_STATIC_DUTY(x) ((x) << 0) argument
215 #define FMAX_DUTY100(x) ((x) << 0) argument
219 #define TMIN(x) ((x) << 0) argument
222 #define FDO_PWM_MODE(x) ((x) << 11) argument
225 #define TACH_PWM_RESP_RATE(x) ((x) << 25) argument
230 # define EDGE_PER_REV(x) ((x) << 0) argument
233 # define TARGET_PERIOD(x) ((x) << 3) argument
237 # define TACH_PERIOD(x) ((x) << 0) argument
244 # define THERMAL_PROTECTION_DIS (1 << 2)
246 # define SW_SMIO_INDEX(x) ((x) << 6) argument
274 # define UTC_0(x) ((x) << 0) argument
276 # define DTC_0(x) ((x) << 10) argument
280 # define BSP(x) ((x) << 0) argument
282 # define BSU(x) ((x) << 16) argument
285 # define CG_R(x) ((x) << 0) argument
287 # define CG_L(x) ((x) << 16) argument
291 # define CG_GICST(x) ((x) << 0) argument
293 # define CG_GIPOT(x) ((x) << 16) argument
297 # define SST(x) ((x) << 0) argument
299 # define SSTU(x) ((x) << 16) argument
303 # define DISP1_GAP(x) ((x) << 0) argument
305 # define DISP2_GAP(x) ((x) << 2) argument
306 # define DISP2_GAP_MASK (3 << 2)
307 # define VBI_TIMER_COUNT(x) ((x) << 4) argument
309 # define VBI_TIMER_UNIT(x) ((x) << 20) argument
311 # define DISP1_GAP_MCHG(x) ((x) << 24) argument
313 # define DISP2_GAP_MCHG(x) ((x) << 26) argument
322 # define CAC_WINDOW(x) ((x) << 0) argument
330 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) argument
373 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) argument
374 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) argument
377 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) argument
378 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) argument
382 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) argument
385 #define INVALIDATE_ONLY_PDE_CACHES 2
387 #define BANK_SELECT(x) ((x) << 0) argument
388 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) argument
389 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
395 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
408 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
427 * bit 2: valid
480 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
501 #define NOOFRANK_SHIFT 2
517 #define STATE0(x) ((x) << 0) argument
520 #define STATE1(x) ((x) << 5) argument
523 #define STATE2(x) ((x) << 10) argument
526 #define STATE3(x) ((x) << 15) argument
598 # define DLL_SPEED(x) ((x) << 0) argument
614 #define BWCTRL(x) ((x) << 20) argument
617 #define VCO_MODE(x) ((x) << 0) argument
619 #define CLKFRAC(x) ((x) << 4) argument
621 #define CLKF(x) ((x) << 16) argument
625 #define YCLK_POST_DIV(x) ((x) << 0) argument
628 #define YCLK_SEL(x) ((x) << 4) argument
632 #define CLKV(x) ((x) << 0) argument
635 #define CLKS(x) ((x) << 0) argument
656 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ argument
659 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ argument
671 # define IH_MC_SWAP(x) ((x) << 1) argument
674 # define IH_MC_SWAP_32BIT 2
677 # define MC_WRREQ_CREDIT(x) ((x) << 15) argument
678 # define MC_WR_CLEAN_CNT(x) ((x) << 20) argument
679 # define MC_VMID(x) ((x) << 25) argument
700 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) argument
705 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) argument
725 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) argument
727 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) argument
728 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) argument
729 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ argument
741 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) argument
742 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) argument
745 * x = legal delay value
752 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) argument
753 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) argument
755 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) argument
757 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) argument
759 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) argument
761 # define DESCRIPTION0(x) (((x) & 0xff) << 0) argument
762 # define DESCRIPTION1(x) (((x) & 0xff) << 8) argument
763 # define DESCRIPTION2(x) (((x) & 0xff) << 16) argument
764 # define DESCRIPTION3(x) (((x) & 0xff) << 24) argument
766 # define DESCRIPTION4(x) (((x) & 0xff) << 0) argument
767 # define DESCRIPTION5(x) (((x) & 0xff) << 8) argument
768 # define DESCRIPTION6(x) (((x) & 0xff) << 16) argument
769 # define DESCRIPTION7(x) (((x) & 0xff) << 24) argument
771 # define DESCRIPTION8(x) (((x) & 0xff) << 0) argument
772 # define DESCRIPTION9(x) (((x) & 0xff) << 8) argument
773 # define DESCRIPTION10(x) (((x) & 0xff) << 16) argument
774 # define DESCRIPTION11(x) (((x) & 0xff) << 24) argument
776 # define DESCRIPTION12(x) (((x) & 0xff) << 0) argument
777 # define DESCRIPTION13(x) (((x) & 0xff) << 8) argument
778 # define DESCRIPTION14(x) (((x) & 0xff) << 16) argument
779 # define DESCRIPTION15(x) (((x) & 0xff) << 24) argument
781 # define DESCRIPTION16(x) (((x) & 0xff) << 0) argument
782 # define DESCRIPTION17(x) (((x) & 0xff) << 8) argument
792 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) argument
801 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) argument
803 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) argument
804 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) argument
827 # define LB_D1_VLINE_INTERRUPT (1 << 2)
836 # define LB_D2_VLINE_INTERRUPT (1 << 2)
842 # define LB_D3_VLINE_INTERRUPT (1 << 2)
847 # define LB_D4_VLINE_INTERRUPT (1 << 2)
852 # define LB_D5_VLINE_INTERRUPT (1 << 2)
857 # define LB_D6_VLINE_INTERRUPT (1 << 2)
901 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) argument
902 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) argument
913 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ argument
922 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) argument
926 * 2 = stream2
933 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
969 #define SE_CB_CLEAN (1 << 2)
983 #define SOFT_RESET_RLC (1 << 2)
997 #define INSTANCE_INDEX(x) ((x) << 0) argument
998 #define SH_INDEX(x) ((x) << 8) argument
999 #define SE_INDEX(x) ((x) << 16) argument
1038 #define ROQ_IB1_START(x) ((x) << 0) argument
1039 #define ROQ_IB2_START(x) ((x) << 8) argument
1041 #define MEQ1_START(x) ((x) << 0) argument
1042 #define MEQ2_START(x) ((x) << 8) argument
1049 #define CACHE_INVALIDATION(x) ((x) << 0) argument
1052 #define VC_AND_TC 2
1053 #define AUTO_INVLD_EN(x) ((x) << 6) argument
1056 #define GS_AUTO 2
1082 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
1089 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
1090 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
1093 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) argument
1094 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) argument
1095 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) argument
1096 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) argument
1105 #define MIN_POWER(x) ((x) << 0) argument
1108 #define MAX_POWER(x) ((x) << 16) argument
1112 #define MAX_POWER_DELTA(x) ((x) << 0) argument
1115 #define STI_SIZE(x) ((x) << 16) argument
1118 #define LTI_RATIO(x) ((x) << 27) argument
1132 #define VTX_DONE_DELAY(x) ((x) << 0) argument
1148 #define BACKEND_DISABLE(x) ((x) << 16) argument
1150 #define NUM_PIPES(x) ((x) << 0) argument
1153 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
1156 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
1159 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
1162 #define NUM_GPUS(x) ((x) << 20) argument
1165 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
1168 #define ROW_SIZE(x) ((x) << 28) argument
1173 # define MICRO_TILE_MODE(x) ((x) << 0) argument
1176 # define ADDR_SURF_DEPTH_MICRO_TILING 2
1177 # define ARRAY_MODE(x) ((x) << 2) argument
1180 # define ARRAY_1D_TILED_THIN1 2
1182 # define PIPE_CONFIG(x) ((x) << 6) argument
1195 # define TILE_SPLIT(x) ((x) << 11) argument
1198 # define ADDR_SURF_TILE_SPLIT_256B 2
1203 # define BANK_WIDTH(x) ((x) << 14) argument
1206 # define ADDR_SURF_BANK_WIDTH_4 2
1208 # define BANK_HEIGHT(x) ((x) << 16) argument
1211 # define ADDR_SURF_BANK_HEIGHT_4 2
1213 # define MACRO_TILE_ASPECT(x) ((x) << 18) argument
1216 # define ADDR_SURF_MACRO_ASPECT_4 2
1218 # define NUM_BANKS(x) ((x) << 20) argument
1221 # define ADDR_SURF_8_BANK 2
1275 #define RB_BUFSZ(x) ((x) << 0) argument
1276 #define RB_BLKSZ(x) ((x) << 8) argument
1277 #define BUF_SWAP_32BIT (2 << 16)
1351 # define GFX_CLOCK_STATUS (1 << 2)
1364 # define RLC_PUD(x) ((x) << 0) argument
1366 # define RLC_PDD(x) ((x) << 8) argument
1368 # define RLC_TTPD(x) ((x) << 16) argument
1370 # define RLC_MSD(x) ((x) << 24) argument
1377 # define MAX_PU_CU(x) ((x) << 0) argument
1381 # define GRBM_REG_SGIT(x) ((x) << 3) argument
1383 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) argument
1400 # define RB_MAP_PKR0(x) ((x) << 0) argument
1402 # define RB_MAP_PKR1(x) ((x) << 2) argument
1403 # define RB_MAP_PKR1_MASK (0x3 << 2)
1406 # define RASTER_CONFIG_RB_MAP_2 2
1408 # define RB_XSEL2(x) ((x) << 4) argument
1412 # define PKR_MAP(x) ((x) << 8) argument
1416 # define RASTER_CONFIG_PKR_MAP_2 2
1418 # define PKR_XSEL(x) ((x) << 10) argument
1420 # define PKR_YSEL(x) ((x) << 12) argument
1422 # define SC_MAP(x) ((x) << 16) argument
1424 # define SC_XSEL(x) ((x) << 18) argument
1426 # define SC_YSEL(x) ((x) << 20) argument
1428 # define SE_MAP(x) ((x) << 24) argument
1432 # define RASTER_CONFIG_SE_MAP_2 2
1434 # define SE_XSEL(x) ((x) << 26) argument
1436 # define SE_YSEL(x) ((x) << 28) argument
1442 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1481 # define LS2_EXIT_TIME(x) ((x) << 17) argument
1487 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) argument
1490 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) argument
1493 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) argument
1497 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) argument
1500 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) argument
1503 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) argument
1508 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) argument
1511 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) argument
1514 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) argument
1518 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) argument
1521 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) argument
1524 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) argument
1544 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1545 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
1554 # define LC_L0S_INACTIVITY(x) ((x) << 8) argument
1557 # define LC_L1_INACTIVITY(x) ((x) << 12) argument
1567 # define LC_LINK_WIDTH_X2 2
1580 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) argument
1584 # define LC_XMIT_N_FTS(x) ((x) << 0) argument
1592 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1602 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1632 # define CG_DT(x) ((x) << 2) argument
1633 # define CG_DT_MASK (0xf << 2)
1634 # define CLK_OD(x) ((x) << 6) argument
1642 # define G_DIV_ID(x) ((x) << 2) argument
1643 # define G_DIV_ID_MASK (0x7 << 2)
1667 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
1668 #define GDS_PARTITION_BASE 2
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
1703 * 2 - tc/l2
1710 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
1713 * 2 - ce
1720 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1723 * 2 - <=
1729 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1733 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1741 * 2. SRC_ADDR_LO or DATA [31:0]
1748 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) argument
1752 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) argument
1756 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) argument
1759 * 2 - DATA
1764 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) argument
1767 * 2 - 8 in 32
1770 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) argument
1773 * 2 - 8 in 32
1809 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) argument
1812 #define EVENT_TYPE(x) ((x) << 0) argument
1813 #define EVENT_INDEX(x) ((x) << 8) argument
1816 * 2 - SAMPLE_PIPELINESTAT
1826 #define DATA_SEL(x) ((x) << 29) argument
1829 * 2 - send 64bit data
1832 #define INT_SEL(x) ((x) << 24) argument
1835 * 2 - interrupt when data write is confirmed
1839 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1880 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1884 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1900 # define SEM_WAIT_INT_ENABLE (1 << 2)
1927 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1955 #define VCE_FME_SOFT_RESET (1 << 2)
2034 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2044 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
2082 #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
2108 #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) argument
2115 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) argument
2118 #define FMT_25FRC_SEL(x) ((x) << 26) argument
2119 #define FMT_50FRC_SEL(x) ((x) << 28) argument
2120 #define FMT_75FRC_SEL(x) ((x) << 30) argument
2136 #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) argument
2139 #define EVERGREEN_GRPH_DEPTH_32BPP 2
2140 #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) argument
2143 #define EVERGREEN_ADDR_SURF_8_BANK 2
2145 #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) argument
2146 #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) argument
2149 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2
2151 #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) argument
2156 #define EVERGREEN_GRPH_FORMAT_ARGB4444 2
2164 #define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
2170 #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) argument
2173 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2
2175 #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) argument
2178 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2
2183 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) argument
2186 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
2188 #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) argument
2191 #define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2
2195 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
2199 #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) argument
2202 # define EVERGREEN_GRPH_ENDIAN_8IN32 2
2204 #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) argument
2207 # define EVERGREEN_GRPH_RED_SEL_B 2
2209 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) argument
2212 # define EVERGREEN_GRPH_GREEN_SEL_A 2
2214 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) argument
2217 # define EVERGREEN_GRPH_BLUE_SEL_R 2
2219 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) argument
2222 # define EVERGREEN_GRPH_ALPHA_SEL_G 2
2245 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2257 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) argument
2260 # define EVERGREEN_CURSOR_24_8_PRE_MULT 2
2264 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) argument
2267 # define EVERGREEN_CURSOR_URGENT_1_4 2
2286 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) argument
2289 # define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2
2290 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) argument
2293 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) argument
2296 # define NI_OUTPUT_CSC_YCBCR_601 2
2300 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) argument
2303 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) argument
2306 # define NI_DEGAMMA_XVYCC_222 2
2307 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) argument
2308 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) argument
2309 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) argument
2312 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) argument
2315 # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2
2317 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) argument
2320 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) argument
2323 # define NI_REGAMMA_XVYCC_222 2
2326 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) argument
2336 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) argument
2339 # define NI_INPUT_GAMMA_SRGB_24 2
2341 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) argument
2370 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2449 #define SDMA_MAX_INSTANCE 2
2474 #define VCEPLL_PDIV_A(x) ((x) << 0) argument
2476 #define VCEPLL_PDIV_B(x) ((x) << 8) argument
2478 #define EVCLK_SRC_SEL(x) ((x) << 20) argument
2480 #define ECCLK_SRC_SEL(x) ((x) << 25) argument
2484 #define VCEPLL_FB_DIV(x) ((x) << 0) argument