Lines Matching +full:1 +full:x
57 # define AUTO_INCREMENT_IND_0 (1 << 0)
70 # define RST_REG (1 << 0)
72 # define CK_DISABLE (1 << 0)
73 # define CKEN (1 << 24)
76 #define VGA_MEMORY_DISABLE (1 << 4)
79 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
82 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
87 #define SPLL_RESET (1 << 0)
88 #define SPLL_SLEEP (1 << 1)
89 #define SPLL_BYPASS_EN (1 << 3)
90 #define SPLL_REF_DIV(x) ((x) << 4) argument
92 #define SPLL_PDIV_A(x) ((x) << 20) argument
96 #define SCLK_MUX_SEL(x) ((x) << 0) argument
98 #define SPLL_CTLREQ_CHG (1 << 23)
99 #define SCLK_MUX_UPDATE (1 << 26)
101 #define SPLL_FB_DIV(x) ((x) << 0) argument
104 #define SPLL_DITHEN (1 << 28)
108 #define SPLL_CHG_STATUS (1 << 1)
110 #define SPLL_SW_DIR_CONTROL (1 << 0)
111 # define SPLL_REFCLK_SEL(x) ((x) << 26) argument
115 #define SSEN (1 << 0)
116 #define CLK_S(x) ((x) << 4) argument
120 #define CLK_V(x) ((x) << 0) argument
125 # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
138 # define UPLL_PDIV_A(x) ((x) << 0) argument
140 # define UPLL_PDIV_B(x) ((x) << 8) argument
142 # define VCLK_SRC_SEL(x) ((x) << 20) argument
144 # define DCLK_SRC_SEL(x) ((x) << 25) argument
147 # define UPLL_FB_DIV(x) ((x) << 0) argument
157 # define MPLL_CLKOUT_SEL(x) ((x) << 8) argument
161 # define XTALIN_DIVIDE (1 << 1)
162 # define BCLK_AS_XCLK (1 << 2)
164 # define FORCE_BIF_REFCLK_EN (1 << 3)
165 # define MUX_TCLK_TO_XCLK (1 << 8)
168 # define CMON_CLK_SEL(x) ((x) << 0) argument
170 # define TMON_CLK_SEL(x) ((x) << 8) argument
173 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) argument
175 # define ZCLK_SEL(x) ((x) << 8) argument
179 #define DPM_EVENT_SRC(x) ((x) << 0) argument
181 #define DIG_THERM_DPM(x) ((x) << 14) argument
185 #define FDO_PWM_DUTY(x) ((x) << 9) argument
189 #define DIG_THERM_INTH(x) ((x) << 8) argument
192 #define DIG_THERM_INTL(x) ((x) << 16) argument
195 #define THERM_INT_MASK_HIGH (1 << 24)
196 #define THERM_INT_MASK_LOW (1 << 25)
199 #define TEMP_SEL(x) ((x) << 20) argument
203 #define ASIC_MAX_TEMP(x) ((x) << 0) argument
206 #define CTF_TEMP(x) ((x) << 9) argument
211 #define FDO_STATIC_DUTY(x) ((x) << 0) argument
215 #define FMAX_DUTY100(x) ((x) << 0) argument
219 #define TMIN(x) ((x) << 0) argument
222 #define FDO_PWM_MODE(x) ((x) << 11) argument
225 #define TACH_PWM_RESP_RATE(x) ((x) << 25) argument
230 # define EDGE_PER_REV(x) ((x) << 0) argument
233 # define TARGET_PERIOD(x) ((x) << 3) argument
237 # define TACH_PERIOD(x) ((x) << 0) argument
242 # define GLOBAL_PWRMGT_EN (1 << 0)
243 # define STATIC_PM_EN (1 << 1)
244 # define THERMAL_PROTECTION_DIS (1 << 2)
245 # define THERMAL_PROTECTION_TYPE (1 << 3)
246 # define SW_SMIO_INDEX(x) ((x) << 6) argument
247 # define SW_SMIO_INDEX_MASK (1 << 6)
249 # define VOLT_PWRMGT_EN (1 << 10)
250 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
253 # define SCLK_PWRMGT_OFF (1 << 0)
254 # define SCLK_LOW_D1 (1 << 1)
255 # define FIR_RESET (1 << 4)
256 # define FIR_FORCE_TREND_SEL (1 << 5)
257 # define FIR_TREND_MODE (1 << 6)
258 # define DYN_GFX_CLK_OFF_EN (1 << 7)
259 # define GFX_CLK_FORCE_ON (1 << 8)
260 # define GFX_CLK_REQUEST_OFF (1 << 9)
261 # define GFX_CLK_FORCE_OFF (1 << 10)
262 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
263 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
264 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
265 # define DYN_LIGHT_SLEEP_EN (1 << 14)
274 # define UTC_0(x) ((x) << 0) argument
276 # define DTC_0(x) ((x) << 10) argument
280 # define BSP(x) ((x) << 0) argument
282 # define BSU(x) ((x) << 16) argument
285 # define CG_R(x) ((x) << 0) argument
287 # define CG_L(x) ((x) << 16) argument
291 # define CG_GICST(x) ((x) << 0) argument
293 # define CG_GIPOT(x) ((x) << 16) argument
297 # define SST(x) ((x) << 0) argument
299 # define SSTU(x) ((x) << 16) argument
303 # define DISP1_GAP(x) ((x) << 0) argument
305 # define DISP2_GAP(x) ((x) << 2) argument
307 # define VBI_TIMER_COUNT(x) ((x) << 4) argument
309 # define VBI_TIMER_UNIT(x) ((x) << 20) argument
311 # define DISP1_GAP_MCHG(x) ((x) << 24) argument
313 # define DISP2_GAP_MCHG(x) ((x) << 26) argument
322 # define CAC_WINDOW(x) ((x) << 0) argument
330 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) argument
331 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
334 #define GRBM_RQ_PENDING (1 << 5)
335 #define VMC_BUSY (1 << 8)
336 #define MCB_BUSY (1 << 9)
337 #define MCB_NON_DISPLAY_BUSY (1 << 10)
338 #define MCC_BUSY (1 << 11)
339 #define MCD_BUSY (1 << 12)
340 #define SEM_BUSY (1 << 14)
341 #define IH_BUSY (1 << 17)
344 #define SOFT_RESET_BIF (1 << 1)
345 #define SOFT_RESET_DC (1 << 5)
346 #define SOFT_RESET_DMA1 (1 << 6)
347 #define SOFT_RESET_GRBM (1 << 8)
348 #define SOFT_RESET_HDP (1 << 9)
349 #define SOFT_RESET_IH (1 << 10)
350 #define SOFT_RESET_MC (1 << 11)
351 #define SOFT_RESET_ROM (1 << 14)
352 #define SOFT_RESET_SEM (1 << 15)
353 #define SOFT_RESET_VMC (1 << 17)
354 #define SOFT_RESET_DMA (1 << 20)
355 #define SOFT_RESET_TST (1 << 21)
356 #define SOFT_RESET_REGBB (1 << 22)
357 #define SOFT_RESET_ORB (1 << 23)
367 #define DMA_BUSY (1 << 5)
368 #define DMA1_BUSY (1 << 6)
371 #define ENABLE_L2_CACHE (1 << 0)
372 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
373 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) argument
374 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) argument
375 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
377 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) argument
378 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) argument
380 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
381 #define INVALIDATE_L2_CACHE (1 << 1)
382 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) argument
384 #define INVALIDATE_ONLY_PTE_CACHES 1
387 #define BANK_SELECT(x) ((x) << 0) argument
388 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) argument
389 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
390 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
392 #define L2_BUSY (1 << 0)
394 #define ENABLE_CONTEXT (1 << 0)
395 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
396 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
397 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
398 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
399 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
400 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
401 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
402 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
403 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
404 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
405 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
406 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
407 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
408 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
426 * bit 1: pde0
433 #define MEMORY_CLIENT_RW_MASK (1 << 24)
459 #define MC_CG_ENABLE (1 << 18)
460 #define MC_LS_ENABLE (1 << 19)
476 #define ENABLE_L1_TLB (1 << 0)
477 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
479 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
483 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
509 #define CHANSIZE_OVERRIDE (1 << 11)
517 #define STATE0(x) ((x) << 0) argument
520 #define STATE1(x) ((x) << 5) argument
523 #define STATE2(x) ((x) << 10) argument
526 #define STATE3(x) ((x) << 15) argument
531 #define TRAIN_DONE_D0 (1 << 30)
532 #define TRAIN_DONE_D1 (1 << 31)
535 #define RUN_MASK (1 << 0)
540 #define MEM_FALL_OUT_CMD (1 << 8)
558 #define MC_SEQ_MISC0_REV_ID_VALUE 1
598 # define DLL_SPEED(x) ((x) << 0) argument
600 # define DLL_READY (1 << 6)
601 # define MC_INT_CNTL (1 << 7)
602 # define MRDCK0_PDNB (1 << 8)
603 # define MRDCK1_PDNB (1 << 9)
604 # define MRDCK0_RESET (1 << 16)
605 # define MRDCK1_RESET (1 << 17)
606 # define DLL_READY_READ (1 << 24)
608 # define MRDCK0_BYPASS (1 << 24)
609 # define MRDCK1_BYPASS (1 << 25)
612 # define MPLL_MCLK_SEL (1 << 11)
614 #define BWCTRL(x) ((x) << 20) argument
617 #define VCO_MODE(x) ((x) << 0) argument
619 #define CLKFRAC(x) ((x) << 4) argument
621 #define CLKF(x) ((x) << 16) argument
625 #define YCLK_POST_DIV(x) ((x) << 0) argument
628 #define YCLK_SEL(x) ((x) << 4) argument
629 #define YCLK_SEL_MASK (1 << 4)
632 #define CLKV(x) ((x) << 0) argument
635 #define CLKS(x) ((x) << 0) argument
639 #define CLOCK_GATING_DIS (1 << 23)
648 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
650 #define HDP_LS_ENABLE (1 << 0)
655 # define IH_RB_ENABLE (1 << 0)
656 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ argument
657 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
658 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
659 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ argument
660 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
661 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
665 # define RB_OVERFLOW (1 << 0)
670 # define ENABLE_INTR (1 << 0)
671 # define IH_MC_SWAP(x) ((x) << 1) argument
673 # define IH_MC_SWAP_16BIT 1
676 # define RPTR_REARM (1 << 4)
677 # define MC_WRREQ_CREDIT(x) ((x) << 15) argument
678 # define MC_WR_CLEAN_CNT(x) ((x) << 20) argument
679 # define MC_VMID(x) ((x) << 25) argument
684 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
685 # define IH_DUMMY_RD_EN (1 << 1)
686 # define IH_REQ_NONSNOOP_EN (1 << 3)
687 # define GEN_IH_INT_EN (1 << 8)
693 #define FB_READ_EN (1 << 0)
694 #define FB_WRITE_EN (1 << 1)
700 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) argument
701 # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
705 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) argument
708 #define HDMI_CONNECTION (1 << 16)
709 #define DP_CONNECTION (1 << 17)
725 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) argument
727 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) argument
728 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) argument
729 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ argument
741 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) argument
742 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) argument
745 * x = legal delay value
749 # define HBR_CAPABLE (1 << 0) /* enabled by default */
752 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) argument
753 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) argument
755 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) argument
757 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) argument
759 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) argument
761 # define DESCRIPTION0(x) (((x) & 0xff) << 0) argument
762 # define DESCRIPTION1(x) (((x) & 0xff) << 8) argument
763 # define DESCRIPTION2(x) (((x) & 0xff) << 16) argument
764 # define DESCRIPTION3(x) (((x) & 0xff) << 24) argument
766 # define DESCRIPTION4(x) (((x) & 0xff) << 0) argument
767 # define DESCRIPTION5(x) (((x) & 0xff) << 8) argument
768 # define DESCRIPTION6(x) (((x) & 0xff) << 16) argument
769 # define DESCRIPTION7(x) (((x) & 0xff) << 24) argument
771 # define DESCRIPTION8(x) (((x) & 0xff) << 0) argument
772 # define DESCRIPTION9(x) (((x) & 0xff) << 8) argument
773 # define DESCRIPTION10(x) (((x) & 0xff) << 16) argument
774 # define DESCRIPTION11(x) (((x) & 0xff) << 24) argument
776 # define DESCRIPTION12(x) (((x) & 0xff) << 0) argument
777 # define DESCRIPTION13(x) (((x) & 0xff) << 8) argument
778 # define DESCRIPTION14(x) (((x) & 0xff) << 16) argument
779 # define DESCRIPTION15(x) (((x) & 0xff) << 24) argument
781 # define DESCRIPTION16(x) (((x) & 0xff) << 0) argument
782 # define DESCRIPTION17(x) (((x) & 0xff) << 8) argument
785 # define AUDIO_ENABLED (1 << 31)
792 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) argument
796 #define PRIORITY_OFF (1 << 16)
797 #define PRIORITY_ALWAYS_ON (1 << 20)
801 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) argument
803 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) argument
804 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) argument
808 # define VLINE_OCCURRED (1 << 0)
809 # define VLINE_ACK (1 << 4)
810 # define VLINE_STAT (1 << 12)
811 # define VLINE_INTERRUPT (1 << 16)
812 # define VLINE_INTERRUPT_TYPE (1 << 17)
815 # define VBLANK_OCCURRED (1 << 0)
816 # define VBLANK_ACK (1 << 4)
817 # define VBLANK_STAT (1 << 12)
818 # define VBLANK_INTERRUPT (1 << 16)
819 # define VBLANK_INTERRUPT_TYPE (1 << 17)
823 # define VBLANK_INT_MASK (1 << 0)
824 # define VLINE_INT_MASK (1 << 4)
827 # define LB_D1_VLINE_INTERRUPT (1 << 2)
828 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
829 # define DC_HPD1_INTERRUPT (1 << 17)
830 # define DC_HPD1_RX_INTERRUPT (1 << 18)
831 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
832 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
833 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
834 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
836 # define LB_D2_VLINE_INTERRUPT (1 << 2)
837 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
838 # define DC_HPD2_INTERRUPT (1 << 17)
839 # define DC_HPD2_RX_INTERRUPT (1 << 18)
840 # define DISP_TIMER_INTERRUPT (1 << 24)
842 # define LB_D3_VLINE_INTERRUPT (1 << 2)
843 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
844 # define DC_HPD3_INTERRUPT (1 << 17)
845 # define DC_HPD3_RX_INTERRUPT (1 << 18)
847 # define LB_D4_VLINE_INTERRUPT (1 << 2)
848 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
849 # define DC_HPD4_INTERRUPT (1 << 17)
850 # define DC_HPD4_RX_INTERRUPT (1 << 18)
852 # define LB_D5_VLINE_INTERRUPT (1 << 2)
853 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
854 # define DC_HPD5_INTERRUPT (1 << 17)
855 # define DC_HPD5_RX_INTERRUPT (1 << 18)
857 # define LB_D6_VLINE_INTERRUPT (1 << 2)
858 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
859 # define DC_HPD6_INTERRUPT (1 << 17)
860 # define DC_HPD6_RX_INTERRUPT (1 << 18)
864 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
865 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
868 # define GRPH_PFLIP_INT_MASK (1 << 0)
869 # define GRPH_PFLIP_INT_TYPE (1 << 8)
879 # define DC_HPDx_INT_STATUS (1 << 0)
880 # define DC_HPDx_SENSE (1 << 1)
881 # define DC_HPDx_RX_INT_STATUS (1 << 8)
889 # define DC_HPDx_INT_ACK (1 << 0)
890 # define DC_HPDx_INT_POLARITY (1 << 8)
891 # define DC_HPDx_INT_EN (1 << 16)
892 # define DC_HPDx_RX_INT_ACK (1 << 20)
893 # define DC_HPDx_RX_INT_EN (1 << 24)
901 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) argument
902 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) argument
903 # define DC_HPDx_EN (1 << 28)
906 # define STUTTER_ENABLE (1 << 0)
913 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ argument
914 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
922 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) argument
925 * 1 = stream1
933 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
936 #define RLC_RQ_PENDING (1 << 0)
937 #define RLC_BUSY (1 << 8)
938 #define TC_BUSY (1 << 9)
942 #define RING2_RQ_PENDING (1 << 4)
943 #define SRBM_RQ_PENDING (1 << 5)
944 #define RING1_RQ_PENDING (1 << 6)
945 #define CF_RQ_PENDING (1 << 7)
946 #define PF_RQ_PENDING (1 << 8)
947 #define GDS_DMA_RQ_PENDING (1 << 9)
948 #define GRBM_EE_BUSY (1 << 10)
949 #define DB_CLEAN (1 << 12)
950 #define CB_CLEAN (1 << 13)
951 #define TA_BUSY (1 << 14)
952 #define GDS_BUSY (1 << 15)
953 #define VGT_BUSY (1 << 17)
954 #define IA_BUSY_NO_DMA (1 << 18)
955 #define IA_BUSY (1 << 19)
956 #define SX_BUSY (1 << 20)
957 #define SPI_BUSY (1 << 22)
958 #define BCI_BUSY (1 << 23)
959 #define SC_BUSY (1 << 24)
960 #define PA_BUSY (1 << 25)
961 #define DB_BUSY (1 << 26)
962 #define CP_COHERENCY_BUSY (1 << 28)
963 #define CP_BUSY (1 << 29)
964 #define CB_BUSY (1 << 30)
965 #define GUI_ACTIVE (1 << 31)
968 #define SE_DB_CLEAN (1 << 1)
969 #define SE_CB_CLEAN (1 << 2)
970 #define SE_BCI_BUSY (1 << 22)
971 #define SE_VGT_BUSY (1 << 23)
972 #define SE_PA_BUSY (1 << 24)
973 #define SE_TA_BUSY (1 << 25)
974 #define SE_SX_BUSY (1 << 26)
975 #define SE_SPI_BUSY (1 << 27)
976 #define SE_SC_BUSY (1 << 29)
977 #define SE_DB_BUSY (1 << 30)
978 #define SE_CB_BUSY (1 << 31)
981 #define SOFT_RESET_CP (1 << 0)
982 #define SOFT_RESET_CB (1 << 1)
983 #define SOFT_RESET_RLC (1 << 2)
984 #define SOFT_RESET_DB (1 << 3)
985 #define SOFT_RESET_GDS (1 << 4)
986 #define SOFT_RESET_PA (1 << 5)
987 #define SOFT_RESET_SC (1 << 6)
988 #define SOFT_RESET_BCI (1 << 7)
989 #define SOFT_RESET_SPI (1 << 8)
990 #define SOFT_RESET_SX (1 << 10)
991 #define SOFT_RESET_TC (1 << 11)
992 #define SOFT_RESET_TA (1 << 12)
993 #define SOFT_RESET_VGT (1 << 14)
994 #define SOFT_RESET_IA (1 << 15)
997 #define INSTANCE_INDEX(x) ((x) << 0) argument
998 #define SH_INDEX(x) ((x) << 8) argument
999 #define SE_INDEX(x) ((x) << 16) argument
1000 #define SH_BROADCAST_WRITES (1 << 29)
1001 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1002 #define SE_BROADCAST_WRITES (1 << 31)
1005 # define RDERR_INT_ENABLE (1 << 0)
1006 # define GUI_IDLE_INT_ENABLE (1 << 19)
1026 #define CP_CE_HALT (1 << 24)
1027 #define CP_PFP_HALT (1 << 26)
1028 #define CP_ME_HALT (1 << 28)
1038 #define ROQ_IB1_START(x) ((x) << 0) argument
1039 #define ROQ_IB2_START(x) ((x) << 8) argument
1041 #define MEQ1_START(x) ((x) << 0) argument
1042 #define MEQ2_START(x) ((x) << 8) argument
1049 #define CACHE_INVALIDATION(x) ((x) << 0) argument
1051 #define TC_ONLY 1
1053 #define AUTO_INVLD_EN(x) ((x) << 6) argument
1055 #define ES_AUTO 1
1081 #define CLIP_VTX_REORDER_ENA (1 << 0)
1082 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
1089 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
1090 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
1093 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) argument
1094 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) argument
1095 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) argument
1096 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) argument
1105 #define MIN_POWER(x) ((x) << 0) argument
1108 #define MAX_POWER(x) ((x) << 16) argument
1112 #define MAX_POWER_DELTA(x) ((x) << 0) argument
1115 #define STI_SIZE(x) ((x) << 16) argument
1118 #define LTI_RATIO(x) ((x) << 27) argument
1132 #define VTX_DONE_DELAY(x) ((x) << 0) argument
1133 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1140 #define OVERRIDE (1 << 21)
1141 #define LS_OVERRIDE (1 << 22)
1148 #define BACKEND_DISABLE(x) ((x) << 16) argument
1150 #define NUM_PIPES(x) ((x) << 0) argument
1153 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
1156 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
1159 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
1162 #define NUM_GPUS(x) ((x) << 20) argument
1165 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
1168 #define ROW_SIZE(x) ((x) << 28) argument
1173 # define MICRO_TILE_MODE(x) ((x) << 0) argument
1175 # define ADDR_SURF_THIN_MICRO_TILING 1
1177 # define ARRAY_MODE(x) ((x) << 2) argument
1179 # define ARRAY_LINEAR_ALIGNED 1
1182 # define PIPE_CONFIG(x) ((x) << 6) argument
1195 # define TILE_SPLIT(x) ((x) << 11) argument
1197 # define ADDR_SURF_TILE_SPLIT_128B 1
1203 # define BANK_WIDTH(x) ((x) << 14) argument
1205 # define ADDR_SURF_BANK_WIDTH_2 1
1208 # define BANK_HEIGHT(x) ((x) << 16) argument
1210 # define ADDR_SURF_BANK_HEIGHT_2 1
1213 # define MACRO_TILE_ASPECT(x) ((x) << 18) argument
1215 # define ADDR_SURF_MACRO_ASPECT_2 1
1218 # define NUM_BANKS(x) ((x) << 20) argument
1220 # define ADDR_SURF_4_BANK 1
1275 #define RB_BUFSZ(x) ((x) << 0) argument
1276 #define RB_BLKSZ(x) ((x) << 8) argument
1278 #define RB_NO_UPDATE (1 << 27)
1279 #define RB_RPTR_WR_ENA (1 << 31)
1307 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1308 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1309 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1310 # define TIME_STAMP_INT_ENABLE (1 << 26)
1311 # define CP_RINGID2_INT_ENABLE (1 << 29)
1312 # define CP_RINGID1_INT_ENABLE (1 << 30)
1313 # define CP_RINGID0_INT_ENABLE (1 << 31)
1317 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
1318 # define TIME_STAMP_INT_STAT (1 << 26)
1319 # define CP_RINGID2_INT_STAT (1 << 29)
1320 # define CP_RINGID1_INT_STAT (1 << 30)
1321 # define CP_RINGID0_INT_STAT (1 << 31)
1324 # define CP_MEM_LS_EN (1 << 0)
1329 # define RLC_ENABLE (1 << 0)
1333 # define LOAD_BALANCE_ENABLE (1 << 0)
1349 # define RLC_BUSY_STATUS (1 << 0)
1350 # define GFX_POWER_STATUS (1 << 1)
1351 # define GFX_CLOCK_STATUS (1 << 2)
1352 # define GFX_LS_STATUS (1 << 3)
1355 # define GFX_PG_ENABLE (1 << 0)
1356 # define GFX_PG_SRC (1 << 1)
1360 # define CGCG_EN (1 << 0)
1361 # define CGLS_EN (1 << 1)
1364 # define RLC_PUD(x) ((x) << 0) argument
1366 # define RLC_PDD(x) ((x) << 8) argument
1368 # define RLC_TTPD(x) ((x) << 16) argument
1370 # define RLC_MSD(x) ((x) << 24) argument
1377 # define MAX_PU_CU(x) ((x) << 0) argument
1380 # define AUTO_PG_EN (1 << 0)
1381 # define GRBM_REG_SGIT(x) ((x) << 3) argument
1383 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) argument
1400 # define RB_MAP_PKR0(x) ((x) << 0) argument
1402 # define RB_MAP_PKR1(x) ((x) << 2) argument
1405 # define RASTER_CONFIG_RB_MAP_1 1
1408 # define RB_XSEL2(x) ((x) << 4) argument
1410 # define RB_XSEL (1 << 6)
1411 # define RB_YSEL (1 << 7)
1412 # define PKR_MAP(x) ((x) << 8) argument
1415 # define RASTER_CONFIG_PKR_MAP_1 1
1418 # define PKR_XSEL(x) ((x) << 10) argument
1420 # define PKR_YSEL(x) ((x) << 12) argument
1422 # define SC_MAP(x) ((x) << 16) argument
1424 # define SC_XSEL(x) ((x) << 18) argument
1426 # define SC_YSEL(x) ((x) << 20) argument
1428 # define SE_MAP(x) ((x) << 24) argument
1431 # define RASTER_CONFIG_SE_MAP_1 1
1434 # define SE_XSEL(x) ((x) << 26) argument
1436 # define SE_YSEL(x) ((x) << 28) argument
1441 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1481 # define LS2_EXIT_TIME(x) ((x) << 17) argument
1485 # define MULTI_PIF (1 << 25)
1487 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) argument
1490 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) argument
1493 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) argument
1497 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) argument
1500 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) argument
1503 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) argument
1508 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) argument
1511 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) argument
1514 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) argument
1518 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) argument
1521 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) argument
1524 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) argument
1537 # define SLV_MEM_LS_EN (1 << 16)
1538 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1539 # define MST_MEM_LS_EN (1 << 18)
1540 # define REPLAY_MEM_LS_EN (1 << 19)
1542 # define LC_REVERSE_RCVR (1 << 0)
1543 # define LC_REVERSE_XMIT (1 << 1)
1550 # define P_IGNORE_EDB_ERR (1 << 6)
1554 # define LC_L0S_INACTIVITY(x) ((x) << 8) argument
1557 # define LC_L1_INACTIVITY(x) ((x) << 12) argument
1560 # define LC_PMI_TO_L1_DIS (1 << 16)
1561 # define LC_ASPM_TO_L1_DIS (1 << 24)
1566 # define LC_LINK_WIDTH_X1 1
1573 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1574 # define LC_RECONFIG_NOW (1 << 8)
1575 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1576 # define LC_RENEGOTIATE_EN (1 << 10)
1577 # define LC_SHORT_RECONFIG_EN (1 << 11)
1578 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1579 # define LC_UPCONFIGURE_DIS (1 << 13)
1580 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) argument
1584 # define LC_XMIT_N_FTS(x) ((x) << 0) argument
1587 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1590 # define LC_GEN2_EN_STRAP (1 << 0)
1591 # define LC_GEN3_EN_STRAP (1 << 1)
1592 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1595 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1596 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1597 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1598 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1599 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1602 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1604 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1605 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1606 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1607 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1608 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1611 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1612 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1615 # define LC_GO_TO_RECOVERY (1 << 30)
1617 # define LC_REDO_EQ (1 << 5)
1618 # define LC_SET_QUIESCE (1 << 13)
1631 # define DCM (1 << 0)
1632 # define CG_DT(x) ((x) << 2) argument
1634 # define CLK_OD(x) ((x) << 6) argument
1640 # define DYN_OR_EN (1 << 0)
1641 # define DYN_RR_EN (1 << 1)
1642 # define G_DIV_ID(x) ((x) << 2) argument
1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1667 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
1702 * 1 - memory (sync - via GRBM)
1708 #define WR_ONE_ADDR (1 << 16)
1709 #define WR_CONFIRM (1 << 20)
1710 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
1712 * 1 - pfp
1720 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1722 * 1 - <
1729 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1731 * 1 - mem
1733 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1735 * 1 - pfp
1740 /* 1. header
1748 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) argument
1750 * 1 - GDS
1752 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) argument
1754 * 1 - PFP
1756 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) argument
1758 * 1 - GDS
1761 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1763 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1764 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) argument
1766 * 1 - 8 in 16
1770 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) argument
1772 * 1 - 8 in 16
1776 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1778 * 1 - register
1780 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1782 * 1 - register
1784 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1785 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1786 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1789 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1790 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1791 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1792 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1793 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1794 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1795 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1796 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1797 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1798 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1799 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1800 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1801 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1802 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1803 # define PACKET3_TC_ACTION_ENA (1 << 23)
1804 # define PACKET3_CB_ACTION_ENA (1 << 25)
1805 # define PACKET3_DB_ACTION_ENA (1 << 26)
1806 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1807 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1809 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) argument
1812 #define EVENT_TYPE(x) ((x) << 0) argument
1813 #define EVENT_INDEX(x) ((x) << 8) argument
1815 * 1 - ZPASS_DONE
1823 #define INV_L2 (1 << 20)
1826 #define DATA_SEL(x) ((x) << 29) argument
1828 * 1 - send low 32bit data
1832 #define INT_SEL(x) ((x) << 24) argument
1834 * 1 - interrupt only (DATA_SEL = 0)
1879 # define DMA_RB_ENABLE (1 << 0)
1880 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1881 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1882 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1883 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1884 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1893 # define DMA_IB_ENABLE (1 << 0)
1894 # define DMA_IB_SWAP_ENABLE (1 << 4)
1895 # define CMD_VMID_FORCE (1 << 31)
1898 # define TRAP_ENABLE (1 << 0)
1899 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1900 # define SEM_WAIT_INT_ENABLE (1 << 2)
1901 # define DATA_SWAP_ENABLE (1 << 3)
1902 # define FENCE_SWAP_ENABLE (1 << 4)
1903 # define CTXEMPTY_INT_ENABLE (1 << 28)
1905 # define DMA_IDLE (1 << 0)
1909 # define MEM_POWER_OVERRIDE (1 << 8)
1913 # define PG_CNTL_ENABLE (1 << 0)
1928 (1 << 26) | \
1929 (1 << 21) | \
1946 #define VCE_CLK_EN (1 << 0)
1954 #define VCE_ECPU_SOFT_RESET (1 << 0)
1955 #define VCE_FME_SOFT_RESET (1 << 2)
1971 # define VCE_FW_REG_STATUS_BUSY (1 << 0)
1972 # define VCE_FW_REG_STATUS_PASS (1 << 3)
1973 # define VCE_FW_REG_STATUS_DONE (1 << 11)
2012 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
2017 #define EVERGREEN_CRTC_MASTER_EN (1 << 0)
2018 #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2020 #define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
2021 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
2026 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2034 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2037 # define EVERGREEN_INTERLEAVE_EN (1 << 0)
2043 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
2081 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
2086 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
2087 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)
2088 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
2089 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
2090 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
2091 # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24)
2095 # define R600_BIOS_ROM_DIS (1 << 1)
2098 # define R600_SCK_OVERWRITE (1 << 1)
2105 #define FMT_TRUNCATE_EN (1 << 0)
2106 #define FMT_TRUNCATE_DEPTH (1 << 4)
2107 #define FMT_SPATIAL_DITHER_EN (1 << 8)
2108 #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) argument
2109 #define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
2110 #define FMT_FRAME_RANDOM_ENABLE (1 << 13)
2111 #define FMT_RGB_RANDOM_ENABLE (1 << 14)
2112 #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
2113 #define FMT_TEMPORAL_DITHER_EN (1 << 16)
2114 #define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
2115 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) argument
2116 #define FMT_TEMPORAL_LEVEL (1 << 24)
2117 #define FMT_TEMPORAL_DITHER_RESET (1 << 25)
2118 #define FMT_25FRC_SEL(x) ((x) << 26) argument
2119 #define FMT_50FRC_SEL(x) ((x) << 28) argument
2120 #define FMT_75FRC_SEL(x) ((x) << 30) argument
2136 #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) argument
2138 #define EVERGREEN_GRPH_DEPTH_16BPP 1
2140 #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) argument
2142 #define EVERGREEN_ADDR_SURF_4_BANK 1
2145 #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) argument
2146 #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) argument
2148 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1
2151 #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) argument
2155 #define EVERGREEN_GRPH_FORMAT_ARGB565 1
2163 #define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
2170 #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) argument
2172 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1
2175 #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) argument
2177 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1
2183 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) argument
2185 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
2188 #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) argument
2190 #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
2194 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
2199 #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) argument
2201 # define EVERGREEN_GRPH_ENDIAN_8IN16 1
2204 #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) argument
2206 # define EVERGREEN_GRPH_RED_SEL_G 1
2209 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) argument
2211 # define EVERGREEN_GRPH_GREEN_SEL_B 1
2214 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) argument
2216 # define EVERGREEN_GRPH_BLUE_SEL_A 1
2219 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) argument
2221 # define EVERGREEN_GRPH_ALPHA_SEL_R 1
2233 #define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)
2245 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2246 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2248 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
2256 # define EVERGREEN_CURSOR_EN (1 << 0)
2257 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) argument
2259 # define EVERGREEN_CURSOR_24_1 1
2262 # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
2263 # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
2264 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) argument
2266 # define EVERGREEN_CURSOR_URGENT_1_8 1
2279 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
2280 # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
2281 # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
2282 # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
2286 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) argument
2288 # define NI_INPUT_CSC_PROG_COEFF 1
2290 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) argument
2293 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) argument
2295 # define NI_OUTPUT_CSC_TV_RGB 1
2300 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) argument
2303 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) argument
2305 # define NI_DEGAMMA_SRGB_24 1
2307 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) argument
2308 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) argument
2309 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) argument
2312 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) argument
2314 # define NI_GAMUT_REMAP_PROG_COEFF 1
2317 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) argument
2320 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) argument
2322 # define NI_REGAMMA_SRGB_24 1
2326 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) argument
2330 # define NI_GRPH_PRESCALE_BYPASS (1 << 4)
2333 # define NI_OVL_PRESCALE_BYPASS (1 << 4)
2336 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) argument
2338 # define NI_INPUT_GAMMA_BYPASS 1
2341 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) argument
2348 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
2353 # define EVERGREEN_CRTC_MASTER_EN (1 << 0)
2354 # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2356 # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
2357 # define EVERGREEN_CRTC_V_BLANK (1 << 0)
2362 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2370 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2474 #define VCEPLL_PDIV_A(x) ((x) << 0) argument
2476 #define VCEPLL_PDIV_B(x) ((x) << 8) argument
2478 #define EVCLK_SRC_SEL(x) ((x) << 20) argument
2480 #define ECCLK_SRC_SEL(x) ((x) << 25) argument
2484 #define VCEPLL_FB_DIV(x) ((x) << 0) argument