Lines Matching +full:mclk +full:- +full:equal +full:- +full:bclk
992 switch (adev->asic_type) { in si_query_video_codecs()
1014 return -EINVAL; in si_query_video_codecs()
1023 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
1027 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
1035 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
1040 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
1048 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
1052 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
1060 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_wreg()
1065 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_wreg()
1073 spin_lock_irqsave(&adev->smc_idx_lock, flags); in si_smc_rreg()
1076 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in si_smc_rreg()
1084 spin_lock_irqsave(&adev->smc_idx_lock, flags); in si_smc_wreg()
1087 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in si_smc_wreg()
1095 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in si_uvd_ctx_rreg()
1098 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in si_uvd_ctx_rreg()
1106 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in si_uvd_ctx_wreg()
1109 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in si_uvd_ctx_wreg()
1175 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in si_get_register_value()
1177 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in si_get_register_value()
1179 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in si_get_register_value()
1182 mutex_lock(&adev->grbm_idx_mutex); in si_get_register_value()
1190 mutex_unlock(&adev->grbm_idx_mutex); in si_get_register_value()
1197 return adev->gfx.config.gb_addr_config; in si_get_register_value()
1199 return adev->gfx.config.mc_arb_ramcfg; in si_get_register_value()
1232 idx = (reg_offset - mmGB_TILE_MODE0); in si_get_register_value()
1233 return adev->gfx.config.tile_mode_array[idx]; in si_get_register_value()
1255 return -EINVAL; in si_read_register()
1268 if (adev->mode_info.num_crtc) { in si_read_disabled_bios()
1277 if (adev->mode_info.num_crtc) { in si_read_disabled_bios()
1294 if (adev->mode_info.num_crtc) { in si_read_disabled_bios()
1317 if (adev->flags & AMD_IS_APU) in si_read_bios_from_rom()
1342 for (i = 0; i < adev->usec_timeout; i++) { in si_set_clk_bypass_mode()
1381 int r = -EINVAL; in si_gpu_pci_config_reset()
1385 /* set mclk/sclk to bypass */ in si_gpu_pci_config_reset()
1390 pci_clear_master(adev->pdev); in si_gpu_pci_config_reset()
1397 for (i = 0; i < adev->usec_timeout; i++) { in si_gpu_pci_config_reset()
1400 pci_set_master(adev->pdev); in si_gpu_pci_config_reset()
1401 adev->has_hw_reset = true; in si_gpu_pci_config_reset()
1423 amdgpu_reset_method != -1) in si_asic_reset_method()
1424 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in si_asic_reset_method()
1436 dev_info(adev->dev, "PCI reset\n"); in si_asic_reset()
1440 dev_info(adev->dev, "PCI CONFIG reset\n"); in si_asic_reset()
1469 u32 reference_clock = adev->clock.spll.reference_freq; in si_get_xclk()
1485 if (!ring || !ring->funcs->emit_wreg) { in si_flush_hdp()
1496 if (!ring || !ring->funcs->emit_wreg) { in si_invalidate_hdp()
1519 if (adev->flags & AMD_IS_APU) in si_get_pcie_lanes()
1544 if (adev->flags & AMD_IS_APU) in si_set_pcie_lanes()
1590 if (adev->flags & AMD_IS_APU) in si_get_pcie_usage()
1665 return -ETIMEDOUT; in si_uvd_send_upll_ctlreq()
1682 /* We alway need a frequency less than or equal the target */ in si_uvd_calc_upll_post_div()
1694 * si_calc_upll_dividers - calc UPLL clock dividers
1711 * Returns zero on success; -EINVAL on error.
1723 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq; in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1770 return -EINVAL; in si_calc_upll_dividers()
1780 /* Bypass vclk and dclk with bclk */ in si_set_uvd_clocks()
1892 return -ETIMEDOUT; in si_vce_send_vcepll_ctlreq()
1903 /* Bypass evclk and ecclk with bclk */ in si_set_vce_clocks()
2029 adev->smc_rreg = &si_smc_rreg; in si_common_early_init()
2030 adev->smc_wreg = &si_smc_wreg; in si_common_early_init()
2031 adev->pcie_rreg = &si_pcie_rreg; in si_common_early_init()
2032 adev->pcie_wreg = &si_pcie_wreg; in si_common_early_init()
2033 adev->pciep_rreg = &si_pciep_rreg; in si_common_early_init()
2034 adev->pciep_wreg = &si_pciep_wreg; in si_common_early_init()
2035 adev->uvd_ctx_rreg = si_uvd_ctx_rreg; in si_common_early_init()
2036 adev->uvd_ctx_wreg = si_uvd_ctx_wreg; in si_common_early_init()
2037 adev->didt_rreg = NULL; in si_common_early_init()
2038 adev->didt_wreg = NULL; in si_common_early_init()
2040 adev->asic_funcs = &si_asic_funcs; in si_common_early_init()
2042 adev->rev_id = si_get_rev_id(adev); in si_common_early_init()
2043 adev->external_rev_id = 0xFF; in si_common_early_init()
2044 switch (adev->asic_type) { in si_common_early_init()
2046 adev->cg_flags = in si_common_early_init()
2060 adev->pg_flags = 0; in si_common_early_init()
2061 adev->external_rev_id = (adev->rev_id == 0) ? 1 : in si_common_early_init()
2062 (adev->rev_id == 1) ? 5 : 6; in si_common_early_init()
2065 adev->cg_flags = in si_common_early_init()
2081 adev->pg_flags = 0; in si_common_early_init()
2082 adev->external_rev_id = adev->rev_id + 20; in si_common_early_init()
2086 adev->cg_flags = in si_common_early_init()
2102 adev->pg_flags = 0; in si_common_early_init()
2104 adev->external_rev_id = adev->rev_id + 40; in si_common_early_init()
2107 adev->cg_flags = in si_common_early_init()
2122 adev->pg_flags = 0; in si_common_early_init()
2123 adev->external_rev_id = 60; in si_common_early_init()
2126 adev->cg_flags = in si_common_early_init()
2140 adev->pg_flags = 0; in si_common_early_init()
2141 adev->external_rev_id = 70; in si_common_early_init()
2145 return -EINVAL; in si_common_early_init()
2164 switch (adev->asic_type) { in si_init_golden_registers()
2235 struct pci_dev *root = adev->pdev->bus->self; in si_pcie_gen3_enable()
2240 if (pci_is_root_bus(adev->pdev->bus)) in si_pcie_gen3_enable()
2246 if (adev->flags & AMD_IS_APU) in si_pcie_gen3_enable()
2249 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in si_pcie_gen3_enable()
2256 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { in si_pcie_gen3_enable()
2262 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { in si_pcie_gen3_enable()
2270 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) in si_pcie_gen3_enable()
2273 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { in si_pcie_gen3_enable()
2280 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); in si_pcie_gen3_enable()
2297 pcie_capability_read_word(adev->pdev, in si_pcie_gen3_enable()
2305 pcie_capability_read_word(adev->pdev, in si_pcie_gen3_enable()
2311 pcie_capability_read_word(adev->pdev, in si_pcie_gen3_enable()
2329 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, in si_pcie_gen3_enable()
2340 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, in si_pcie_gen3_enable()
2359 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) in si_pcie_gen3_enable()
2361 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) in si_pcie_gen3_enable()
2365 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, in si_pcie_gen3_enable()
2372 for (i = 0; i < adev->usec_timeout; i++) { in si_pcie_gen3_enable()
2385 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pif_phy0_rreg()
2388 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pif_phy0_rreg()
2396 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pif_phy0_wreg()
2399 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pif_phy0_wreg()
2407 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pif_phy1_rreg()
2410 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pif_phy1_rreg()
2418 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pif_phy1_wreg()
2421 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pif_phy1_wreg()
2487 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { in si_program_aspm()
2536 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) in si_program_aspm()
2543 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) in si_program_aspm()
2549 !pci_is_root_bus(adev->pdev->bus)) { in si_program_aspm()
2550 struct pci_dev *root = adev->pdev->bus->self; in si_program_aspm()
2630 readrq = pcie_get_readrq(adev->pdev); in si_fix_pci_max_read_req_size()
2631 v = ffs(readrq) - 8; in si_fix_pci_max_read_req_size()
2633 pcie_set_readrq(adev->pdev, 512); in si_fix_pci_max_read_req_size()
2724 switch (adev->asic_type) { in si_set_ip_blocks()
2734 if (adev->enable_virtual_display) in si_set_ip_blocks()
2752 if (adev->enable_virtual_display) in si_set_ip_blocks()
2770 if (adev->enable_virtual_display) in si_set_ip_blocks()