292 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_init_microcode()
438 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_insert_nop()  local
442 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_insert_nop()
599 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_stop()
658 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_ctx_switch_enable()
700 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_enable()
727 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_resume()
728 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_gfx_resume()
882  * sdma_v5_0_load_microcode - load the sDMA ME ucode
899 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_load_microcode()
900 		if (!adev->sdma.instance[i].fw)  in sdma_v5_0_load_microcode()
903 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v5_0_load_microcode()
908 			(adev->sdma.instance[i].fw->data +  in sdma_v5_0_load_microcode()
919 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v5_0_load_microcode()
954 	/* enable sdma ring preemption */  in sdma_v5_0_start()
1191  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1219  * Update PTEs by writing them manually using sDMA (NAVI10).
1240  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1249  * Update the page tables using sDMA (NAVI10).
1278 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_pad_ib()  local
1284 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_pad_ib()
1321  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1328  * using sDMA (NAVI10).
1396 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1399 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1403 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1406 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1410 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_sw_init()
1411 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_sw_init()
1415 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,  in sdma_v5_0_sw_init()
1423 		sprintf(ring->name, "sdma%d", i);  in sdma_v5_0_sw_init()
1424 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,  in sdma_v5_0_sw_init()
1432 	/* Allocate memory for SDMA IP Dump buffer */  in sdma_v5_0_sw_init()
1433 	ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);  in sdma_v5_0_sw_init()
1435 		adev->sdma.ip_dump = ptr;  in sdma_v5_0_sw_init()
1437 		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");  in sdma_v5_0_sw_init()
1447 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v5_0_sw_fini()
1448 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v5_0_sw_fini()
1452 	kfree(adev->sdma.ip_dump);  in sdma_v5_0_sw_fini()
1501 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_is_idle()
1609 	DRM_DEBUG("IH: SDMA trap\n");  in sdma_v5_0_process_trap_irq()
1630 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v5_0_process_trap_irq()
1646 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v5_0_process_trap_irq()
1676 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_clock_gating()
1678 			/* Enable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1691 			/* Disable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1713 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_light_sleep()
1715 			/* Enable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1722 			/* Disable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1788 	if (!adev->sdma.ip_dump)  in sdma_v5_0_print_ip_state()
1791 	drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);  in sdma_v5_0_print_ip_state()
1792 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_print_ip_state()
1798 				   adev->sdma.ip_dump[instance_offset + j]);  in sdma_v5_0_print_ip_state()
1809 	if (!adev->sdma.ip_dump)  in sdma_v5_0_dump_ip_state()
1813 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_dump_ip_state()
1816 			adev->sdma.ip_dump[instance_offset + j] =  in sdma_v5_0_dump_ip_state()
1883 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_ring_funcs()
1884 		adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;  in sdma_v5_0_set_ring_funcs()
1885 		adev->sdma.instance[i].ring.me = i;  in sdma_v5_0_set_ring_funcs()
1900 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v5_0_set_irq_funcs()
1901 					adev->sdma.num_instances;  in sdma_v5_0_set_irq_funcs()
1902 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1903 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1907  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1937  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1972 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v5_0_set_buffer_funcs()
1989 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_vm_pte_funcs()
1991 				&adev->sdma.instance[i].ring.sched;  in sdma_v5_0_set_vm_pte_funcs()
1993 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v5_0_set_vm_pte_funcs()