Lines Matching full:sdma
34 #include "sdma/sdma_4_4_2_offset.h"
35 #include "sdma/sdma_4_4_2_sh_mask.h"
161 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
190 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
345 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_4_2_ring_insert_nop() local
349 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_4_2_ring_insert_nop()
426 << (ring->me % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_ring_emit_hdp_flush()
486 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; in sdma_v4_4_2_inst_gfx_stop() local
492 sdma[i] = &adev->sdma.instance[i].ring; in sdma_v4_4_2_inst_gfx_stop()
501 if (sdma[i]->use_doorbell) { in sdma_v4_4_2_inst_gfx_stop()
628 if (adev->sdma.has_page_queue) in sdma_v4_4_2_inst_enable()
631 /* SDMA FW needs to respond to FREEZE requests during reset. in sdma_v4_4_2_inst_enable()
676 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; in sdma_v4_4_2_gfx_resume()
764 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; in sdma_v4_4_2_page_resume()
865 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
885 if (!adev->sdma.instance[i].fw) in sdma_v4_4_2_inst_load_microcode()
888 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v4_4_2_inst_load_microcode()
893 (adev->sdma.instance[i].fw->data + in sdma_v4_4_2_inst_load_microcode()
903 adev->sdma.instance[i].fw_version); in sdma_v4_4_2_inst_load_microcode()
929 /* bypass sdma microcode loading on Gopher */ in sdma_v4_4_2_inst_start()
931 adev->sdma.instance[0].fw) { in sdma_v4_4_2_inst_start()
939 /* enable sdma ring preemption */ in sdma_v4_4_2_inst_start()
950 if (adev->sdma.has_page_queue) in sdma_v4_4_2_inst_start()
981 ring = &adev->sdma.instance[i].ring; in sdma_v4_4_2_inst_start()
987 if (adev->sdma.has_page_queue) { in sdma_v4_4_2_inst_start()
988 struct amdgpu_ring *page = &adev->sdma.instance[i].page; in sdma_v4_4_2_inst_start()
1129 * Update PTEs by copying them from the GART using sDMA.
1157 * Update PTEs by writing them manually using sDMA.
1178 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1187 * Update the page tables using sDMA.
1215 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_4_2_ring_pad_ib() local
1221 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_4_2_ring_pad_ib()
1252 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1259 * using sDMA.
1304 adev->sdma.has_page_queue = true; in sdma_v4_4_2_early_init()
1344 /* SDMA trap event */ in sdma_v4_4_2_sw_init()
1345 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { in sdma_v4_4_2_sw_init()
1348 &adev->sdma.trap_irq); in sdma_v4_4_2_sw_init()
1353 /* SDMA SRAM ECC event */ in sdma_v4_4_2_sw_init()
1354 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { in sdma_v4_4_2_sw_init()
1357 &adev->sdma.ecc_irq); in sdma_v4_4_2_sw_init()
1362 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ in sdma_v4_4_2_sw_init()
1363 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { in sdma_v4_4_2_sw_init()
1366 &adev->sdma.vm_hole_irq); in sdma_v4_4_2_sw_init()
1372 &adev->sdma.doorbell_invalid_irq); in sdma_v4_4_2_sw_init()
1378 &adev->sdma.pool_timeout_irq); in sdma_v4_4_2_sw_init()
1384 &adev->sdma.srbm_write_irq); in sdma_v4_4_2_sw_init()
1389 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_init()
1390 ring = &adev->sdma.instance[i].ring; in sdma_v4_4_2_sw_init()
1393 aid_id = adev->sdma.instance[i].aid_id; in sdma_v4_4_2_sw_init()
1395 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, in sdma_v4_4_2_sw_init()
1402 sprintf(ring->name, "sdma%d.%d", aid_id, in sdma_v4_4_2_sw_init()
1403 i % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_sw_init()
1404 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v4_4_2_sw_init()
1410 if (adev->sdma.has_page_queue) { in sdma_v4_4_2_sw_init()
1411 ring = &adev->sdma.instance[i].page; in sdma_v4_4_2_sw_init()
1423 i % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_sw_init()
1425 &adev->sdma.trap_irq, in sdma_v4_4_2_sw_init()
1434 dev_err(adev->dev, "fail to initialize sdma ras block\n"); in sdma_v4_4_2_sw_init()
1438 /* Allocate memory for SDMA IP Dump buffer */ in sdma_v4_4_2_sw_init()
1439 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); in sdma_v4_4_2_sw_init()
1441 adev->sdma.ip_dump = ptr; in sdma_v4_4_2_sw_init()
1443 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); in sdma_v4_4_2_sw_init()
1453 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_fini()
1454 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v4_4_2_sw_fini()
1455 if (adev->sdma.has_page_queue) in sdma_v4_4_2_sw_fini()
1456 amdgpu_ring_fini(&adev->sdma.instance[i].page); in sdma_v4_4_2_sw_fini()
1465 kfree(adev->sdma.ip_dump); in sdma_v4_4_2_sw_fini()
1476 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_hw_init()
1494 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_hw_fini()
1496 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_hw_fini()
1497 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, in sdma_v4_4_2_hw_fini()
1533 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_is_idle()
1546 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; in sdma_v4_4_2_wait_for_idle() local
1550 for (j = 0; j < adev->sdma.num_instances; j++) { in sdma_v4_4_2_wait_for_idle()
1551 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); in sdma_v4_4_2_wait_for_idle()
1552 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) in sdma_v4_4_2_wait_for_idle()
1555 if (j == adev->sdma.num_instances) in sdma_v4_4_2_wait_for_idle()
1590 DRM_DEBUG("IH: SDMA trap\n"); in sdma_v4_4_2_process_trap_irq()
1593 /* Client id gives the SDMA instance in AID. To know the exact SDMA in sdma_v4_4_2_process_trap_irq()
1595 * Match node id with the AID id associated with the SDMA instance. */ in sdma_v4_4_2_process_trap_irq()
1596 for (i = instance; i < adev->sdma.num_instances; in sdma_v4_4_2_process_trap_irq()
1597 i += adev->sdma.num_inst_per_aid) { in sdma_v4_4_2_process_trap_irq()
1598 if (adev->sdma.instance[i].aid_id == in sdma_v4_4_2_process_trap_irq()
1603 if (i >= adev->sdma.num_instances) { in sdma_v4_4_2_process_trap_irq()
1606 "Couldn't find the right sdma instance in trap handler"); in sdma_v4_4_2_process_trap_irq()
1612 amdgpu_fence_process(&adev->sdma.instance[i].ring); in sdma_v4_4_2_process_trap_irq()
1651 DRM_ERROR("Illegal instruction in SDMA command stream\n"); in sdma_v4_4_2_process_illegal_inst_irq()
1659 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); in sdma_v4_4_2_process_illegal_inst_irq()
1688 if (instance < 0 || instance >= adev->sdma.num_instances) { in sdma_v4_4_2_print_iv_entry()
1689 dev_err(adev->dev, "sdma instance invalid %d\n", instance); in sdma_v4_4_2_print_iv_entry()
1697 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", in sdma_v4_4_2_print_iv_entry()
1726 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); in sdma_v4_4_2_process_doorbell_invalid_irq()
1746 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); in sdma_v4_4_2_process_srbm_write_irq()
1763 /* 1-not override: enable sdma mem light sleep */ in sdma_v4_4_2_inst_update_medium_grain_light_sleep()
1771 /* 0-override:disable sdma mem light sleep */ in sdma_v4_4_2_inst_update_medium_grain_light_sleep()
1826 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_set_clockgating_state()
1867 if (!adev->sdma.ip_dump) in sdma_v4_4_2_print_ip_state()
1870 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); in sdma_v4_4_2_print_ip_state()
1871 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_print_ip_state()
1877 adev->sdma.ip_dump[instance_offset + j]); in sdma_v4_4_2_print_ip_state()
1888 if (!adev->sdma.ip_dump) in sdma_v4_4_2_dump_ip_state()
1892 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_dump_ip_state()
1895 adev->sdma.ip_dump[instance_offset + j] = in sdma_v4_4_2_dump_ip_state()
1988 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_set_ring_funcs()
1989 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; in sdma_v4_4_2_set_ring_funcs()
1990 adev->sdma.instance[i].ring.me = i; in sdma_v4_4_2_set_ring_funcs()
1991 if (adev->sdma.has_page_queue) { in sdma_v4_4_2_set_ring_funcs()
1992 adev->sdma.instance[i].page.funcs = in sdma_v4_4_2_set_ring_funcs()
1994 adev->sdma.instance[i].page.me = i; in sdma_v4_4_2_set_ring_funcs()
1998 /* AID to which SDMA belongs depends on physical instance */ in sdma_v4_4_2_set_ring_funcs()
1999 adev->sdma.instance[i].aid_id = in sdma_v4_4_2_set_ring_funcs()
2000 dev_inst / adev->sdma.num_inst_per_aid; in sdma_v4_4_2_set_ring_funcs()
2036 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2037 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2038 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2039 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2040 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2041 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; in sdma_v4_4_2_set_irq_funcs()
2043 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2044 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2045 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2046 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2047 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2048 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2049 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; in sdma_v4_4_2_set_irq_funcs()
2053 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
2083 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
2117 if (adev->sdma.has_page_queue) in sdma_v4_4_2_set_buffer_funcs()
2118 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; in sdma_v4_4_2_set_buffer_funcs()
2120 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v4_4_2_set_buffer_funcs()
2137 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_set_vm_pte_funcs()
2138 if (adev->sdma.has_page_queue) in sdma_v4_4_2_set_vm_pte_funcs()
2139 sched = &adev->sdma.instance[i].page.sched; in sdma_v4_4_2_set_vm_pte_funcs()
2141 sched = &adev->sdma.instance[i].ring.sched; in sdma_v4_4_2_set_vm_pte_funcs()
2144 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v4_4_2_set_vm_pte_funcs()
2176 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, in sdma_v4_4_2_xcp_suspend()
2194 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2233 .die_id = adev->sdma.instance[sdma_inst].aid_id, in sdma_v4_4_2_inst_query_ras_error_count()
2236 /* sdma v4_4_2 doesn't support query ce counts */ in sdma_v4_4_2_inst_query_ras_error_count()
2255 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_query_ras_error_count()
2260 dev_warn(adev->dev, "SDMA RAS is not supported\n"); in sdma_v4_4_2_query_ras_error_count()
2280 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_reset_ras_error_count()
2285 dev_warn(adev->dev, "SDMA RAS is not supported\n"); in sdma_v4_4_2_reset_ras_error_count()
2376 adev->sdma.ras = &sdma_v4_4_2_ras; in sdma_v4_4_2_set_ras_funcs()