125 #define WREG32_SDMA(instance, offset, value) \  macro
607 		WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);  in sdma_v4_0_setup_ulv()
726 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,  in sdma_v4_0_ring_set_wptr()
728 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,  in sdma_v4_0_ring_set_wptr()
777 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,  in sdma_v4_0_page_ring_set_wptr()
779 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,  in sdma_v4_0_page_ring_set_wptr()
930 		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);  in sdma_v4_0_gfx_enable()
933 		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);  in sdma_v4_0_gfx_enable()
965 		WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);  in sdma_v4_0_page_stop()
969 		WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);  in sdma_v4_0_page_stop()
1015 			WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);  in sdma_v4_0_ctx_switch_enable()
1016 			WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);  in sdma_v4_0_ctx_switch_enable()
1017 			WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);  in sdma_v4_0_ctx_switch_enable()
1019 		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);  in sdma_v4_0_ctx_switch_enable()
1029 			WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);  in sdma_v4_0_ctx_switch_enable()
1031 		WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);  in sdma_v4_0_ctx_switch_enable()
1059 		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);  in sdma_v4_0_enable()
1099 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);  in sdma_v4_0_gfx_resume()
1102 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);  in sdma_v4_0_gfx_resume()
1103 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);  in sdma_v4_0_gfx_resume()
1104 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);  in sdma_v4_0_gfx_resume()
1105 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);  in sdma_v4_0_gfx_resume()
1108 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,  in sdma_v4_0_gfx_resume()
1110 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,  in sdma_v4_0_gfx_resume()
1116 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);  in sdma_v4_0_gfx_resume()
1117 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);  in sdma_v4_0_gfx_resume()
1122 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);  in sdma_v4_0_gfx_resume()
1132 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);  in sdma_v4_0_gfx_resume()
1133 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);  in sdma_v4_0_gfx_resume()
1138 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);  in sdma_v4_0_gfx_resume()
1142 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,  in sdma_v4_0_gfx_resume()
1144 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,  in sdma_v4_0_gfx_resume()
1150 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);  in sdma_v4_0_gfx_resume()
1154 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);  in sdma_v4_0_gfx_resume()
1162 	WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);  in sdma_v4_0_gfx_resume()
1184 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);  in sdma_v4_0_page_resume()
1187 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);  in sdma_v4_0_page_resume()
1188 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);  in sdma_v4_0_page_resume()
1189 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);  in sdma_v4_0_page_resume()
1190 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);  in sdma_v4_0_page_resume()
1193 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,  in sdma_v4_0_page_resume()
1195 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,  in sdma_v4_0_page_resume()
1201 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);  in sdma_v4_0_page_resume()
1202 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);  in sdma_v4_0_page_resume()
1207 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);  in sdma_v4_0_page_resume()
1217 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);  in sdma_v4_0_page_resume()
1218 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);  in sdma_v4_0_page_resume()
1224 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);  in sdma_v4_0_page_resume()
1228 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,  in sdma_v4_0_page_resume()
1230 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,  in sdma_v4_0_page_resume()
1236 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);  in sdma_v4_0_page_resume()
1240 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);  in sdma_v4_0_page_resume()
1248 	WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);  in sdma_v4_0_page_resume()
1361 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);  in sdma_v4_0_load_microcode()
1364 			WREG32_SDMA(i, mmSDMA0_UCODE_DATA,  in sdma_v4_0_load_microcode()
1367 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,  in sdma_v4_0_load_microcode()
1408 		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);  in sdma_v4_0_start()
1416 		WREG32_SDMA(i, mmSDMA0_CNTL, temp);  in sdma_v4_0_start()
1422 			WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);  in sdma_v4_0_start()
2069 	WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);  in sdma_v4_0_set_trap_irq_state()
2159 	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);  in sdma_v4_0_set_ecc_irq_state()
2254 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);  in sdma_v4_0_update_medium_grain_clock_gating()
2268 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);  in sdma_v4_0_update_medium_grain_clock_gating()
2287 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);  in sdma_v4_0_update_medium_grain_light_sleep()
2295 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);  in sdma_v4_0_update_medium_grain_light_sleep()