127 #define RREG32_SDMA(instance, offset) \  macro
605 		temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);  in sdma_v4_0_setup_ulv()
681 		wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);  in sdma_v4_0_ring_get_wptr()
683 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);  in sdma_v4_0_ring_get_wptr()
749 		wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);  in sdma_v4_0_page_ring_get_wptr()
751 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);  in sdma_v4_0_page_ring_get_wptr()
928 		rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);  in sdma_v4_0_gfx_enable()
931 		ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);  in sdma_v4_0_gfx_enable()
962 		rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);  in sdma_v4_0_page_stop()
966 		ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);  in sdma_v4_0_page_stop()
1011 		f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);  in sdma_v4_0_ctx_switch_enable()
1057 		f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);  in sdma_v4_0_enable()
1097 	rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);  in sdma_v4_0_gfx_resume()
1124 	doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);  in sdma_v4_0_gfx_resume()
1125 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);  in sdma_v4_0_gfx_resume()
1146 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);  in sdma_v4_0_gfx_resume()
1156 	ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);  in sdma_v4_0_gfx_resume()
1182 	rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);  in sdma_v4_0_page_resume()
1209 	doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);  in sdma_v4_0_page_resume()
1210 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);  in sdma_v4_0_page_resume()
1232 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);  in sdma_v4_0_page_resume()
1242 	ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);  in sdma_v4_0_page_resume()
1414 		temp = RREG32_SDMA(i, mmSDMA0_CNTL);  in sdma_v4_0_start()
1420 			temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);  in sdma_v4_0_start()
2024 		u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);  in sdma_v4_0_is_idle()
2041 			sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);  in sdma_v4_0_wait_for_idle()
2066 	sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);  in sdma_v4_0_set_trap_irq_state()
2156 	sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);  in sdma_v4_0_set_ecc_irq_state()
2244 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);  in sdma_v4_0_update_medium_grain_clock_gating()
2258 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);  in sdma_v4_0_update_medium_grain_clock_gating()
2284 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);  in sdma_v4_0_update_medium_grain_light_sleep()
2292 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);  in sdma_v4_0_update_medium_grain_light_sleep()
2675 	reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);  in sdma_v4_0_query_ras_error_count_by_instance()
2709 			RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);  in sdma_v4_0_reset_ras_error_count()