Lines Matching +full:address +full:- +full:aligned
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
108 /* PSP boot config sub-commands */
125 …hy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligne…
126 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
128 …_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned…
129 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
151 … buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned…
152 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
185 … buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned…
186 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
190 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/
191 uint32_t virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/
196 …_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned…
197 …uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffe…
204 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
205 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
206 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
207 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
208 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
209 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
210 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
211 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
214 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
215 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
226 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
227 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
284 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */
307 … fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned…
308 …uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
318 …e_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must b…
319 …uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as…
333 …toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned…
334 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
342 …enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process com…
375 /* Command-specific response for Fw Attestation Db */
382 /* Command-specific response for boot config. */
387 /* Union of command-specific responses for GPCOM ring. */
402 …uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw co…
403 …uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw c…
408 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */
424 …sp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB align…
425 …uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer …
431 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
438 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
449 …md_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB align…
450 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
452 …uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame …
453 …uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame…