amd/amdgpu/psp_gfx_if.h

69     volatile uint32_t   rbi_wptr;         /* +4   Write pointer (index) of RBI ring */
125 …ddr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
128 …f_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
130 …_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
151 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
153 …uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bi…
166 …e;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
185 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
187     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
196 …y_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
207 	GFX_FW_TYPE_CP_MEC      = 4,    /* CP-MEC FW                VG + RV */
307 …  fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
318 …; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
333 …_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
401     uint32_t	session_id;	/* +4  session ID in response to LoadTa command */
419 …uint32_t        buf_version;        /* +4  version of the buffer strusture; must be PSP_GFX_CMD_BU…
424 …f_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
449 …f_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
450     uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of GPU Virtual address of command buffer */