amd/amdgpu/psp_gfx_if.h

74 …volatile uint32_t   ring_addr_hi;     /* +24  bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
125 …ddr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
126 …uint32_t        app_phy_addr_hi;        /* bits [63:32] of the GPU Virtual address of the TA binar…
128 …f_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
129 …uint32_t        cmd_buf_phy_addr_hi;    /* bits [63:32] of the GPU Virtual address of CMD buffer */
130 …_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
151 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
152     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of the buffer */
153 …uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bi…
166 …e;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
185 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
186     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of TMR buffer */
187     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
196 …y_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
197 …uint32_t        system_phy_addr_hi;        /* bits [63:32] of system physical address of TMR buffe…
235 	GFX_FW_TYPE_SDMA1_JT                        = 32,   /* SDNA1 JT                 NV      */
307 …  fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
308 …uint32_t                fw_phy_addr_hi;    /* bits [63:32] of GPU Virtual address of FW location */
318 …; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
319 …uint32_t                save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as…
333 …_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
334     uint32_t        toc_phy_addr_hi;        /* bits [63:32] of GPU Virtual address of FW location */
403 …uint32_t	fw_addr_hi;	/* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw c…
424 …f_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
425 …uint32_t        resp_buf_addr_hi;   /* +16 bits [63:32] of GPU Virtual address of response buffer …
449 …f_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
450     uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of GPU Virtual address of command buffer */
453 …uint32_t    fence_addr_hi;      /* +16 bits [63:32] of GPU Virtual address of Fence for this frame…
456     uint32_t    sid_hi;             /* +28 bits [63:32] of SID value (used only for RBI frames) */
457 …uint8_t     vmid;               /* +32 VMID value used for mapping of all addresses for this frame…