Lines Matching +full:2 +full:x
32 #define PACKET_TYPE2 2
57 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
92 * 2 - gl2
99 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
103 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
106 * 2 - ce
117 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
120 * 2 - <=
126 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
130 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
134 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
140 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
143 * 2 - Bypass
145 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
146 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) argument
155 #define EVENT_TYPE(x) ((x) << 0) argument
156 #define EVENT_INDEX(x) ((x) << 8) argument
159 * 2 - SAMPLE_PIPELINESTAT
166 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) argument
167 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) argument
178 #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) argument
181 * 2 - cache_policy__me_release_mem__noa
186 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) argument
189 * 2 - send 64bit data
193 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) argument
196 * 2 - interrupt when data write is confirmed
198 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) argument
206 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
210 * 2. CONTROL
218 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
222 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
226 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
231 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
235 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
238 * 2 - DATA
260 * 2. COHER_CNTL [30:0]
262 * 2. COHER_SIZE [31:0]
269 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) argument
273 * 2:RANGE
276 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) argument
280 * 2:RANGE
283 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) argument
284 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) argument
285 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) argument
286 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) argument
287 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) argument
288 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) argument
289 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) argument
290 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) argument
294 * 2:RANGE
297 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) argument
298 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) argument
299 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) argument
300 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) argument
304 * 2: REVERSE
358 # define FRAME_CMD(x) ((x) << 28) argument
360 * x=0: tmz_begin
361 * x=1: tmz_end
369 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) argument
370 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) argument
371 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) argument
381 * 2. CONTROL
389 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) argument
390 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) argument
391 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) argument
395 * 2. CONTROL
403 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
404 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) argument
405 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) argument
406 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) argument
407 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) argument
408 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) argument
409 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) argument
410 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
411 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
413 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) argument
414 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) argument
417 * 2. CONTROL
424 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) argument
427 * 2 - DISABLE_PROCESS_QUEUES
430 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
431 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
432 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
434 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) argument
436 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) argument
438 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) argument
440 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) argument
442 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) argument
444 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) argument
447 * 2. CONTROL
455 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) argument
456 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) argument
457 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) argument
459 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) argument
461 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) argument
462 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) argument
467 # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) argument