Lines Matching +full:0 +full:x1a000
33 #define NPS_MODE_MASK 0x000000FFL
35 /* Core 0 Port 0 counter */
36 #define smnPCIEP_NAK_COUNTER 0x1A340218
40 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, in nbio_v7_9_remap_hdp_registers()
42 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, in nbio_v7_9_remap_hdp_registers()
50 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); in nbio_v7_9_get_rev_id()
56 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_9_get_rev_id()
66 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, in nbio_v7_9_mc_access_enable()
69 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); in nbio_v7_9_mc_access_enable()
74 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v7_9_get_memsize()
80 u32 doorbell_range = 0, doorbell_ctrl = 0; in nbio_v7_9_sdma_doorbell_range()
103 case 0: in nbio_v7_9_sdma_doorbell_range()
104 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, in nbio_v7_9_sdma_doorbell_range()
109 S2A_DOORBELL_PORT1_AWID, 0xe); in nbio_v7_9_sdma_doorbell_range()
112 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); in nbio_v7_9_sdma_doorbell_range()
116 0x1); in nbio_v7_9_sdma_doorbell_range()
121 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, in nbio_v7_9_sdma_doorbell_range()
126 S2A_DOORBELL_PORT1_AWID, 0x8); in nbio_v7_9_sdma_doorbell_range()
129 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); in nbio_v7_9_sdma_doorbell_range()
133 0x2); in nbio_v7_9_sdma_doorbell_range()
138 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, in nbio_v7_9_sdma_doorbell_range()
143 S2A_DOORBELL_PORT1_AWID, 0x9); in nbio_v7_9_sdma_doorbell_range()
146 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); in nbio_v7_9_sdma_doorbell_range()
150 0x8); in nbio_v7_9_sdma_doorbell_range()
155 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, in nbio_v7_9_sdma_doorbell_range()
160 S2A_DOORBELL_PORT1_AWID, 0xa); in nbio_v7_9_sdma_doorbell_range()
163 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); in nbio_v7_9_sdma_doorbell_range()
167 0x9); in nbio_v7_9_sdma_doorbell_range()
179 u32 doorbell_range = 0, doorbell_ctrl = 0; in nbio_v7_9_vcn_doorbell_range()
190 0x9); in nbio_v7_9_vcn_doorbell_range()
195 0x4); in nbio_v7_9_vcn_doorbell_range()
202 S2A_DOORBELL_PORT1_AWID, 0x4); in nbio_v7_9_vcn_doorbell_range()
205 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); in nbio_v7_9_vcn_doorbell_range()
208 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9); in nbio_v7_9_vcn_doorbell_range()
211 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); in nbio_v7_9_vcn_doorbell_range()
213 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, in nbio_v7_9_vcn_doorbell_range()
220 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); in nbio_v7_9_vcn_doorbell_range()
223 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); in nbio_v7_9_vcn_doorbell_range()
225 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, in nbio_v7_9_vcn_doorbell_range()
236 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); in nbio_v7_9_enable_doorbell_aperture()
237 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v7_9_enable_doorbell_aperture()
238 BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_9_enable_doorbell_aperture()
244 u32 tmp = 0; in nbio_v7_9_enable_doorbell_selfring_aperture()
252 DOORBELL_SELFRING_GPA_APER_SIZE, 0); in nbio_v7_9_enable_doorbell_selfring_aperture()
254 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v7_9_enable_doorbell_selfring_aperture()
256 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v7_9_enable_doorbell_selfring_aperture()
260 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v7_9_enable_doorbell_selfring_aperture()
266 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; in nbio_v7_9_ih_doorbell_range()
276 0x8); in nbio_v7_9_ih_doorbell_range()
283 S2A_DOORBELL_PORT1_AWID, 0); in nbio_v7_9_ih_doorbell_range()
286 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); in nbio_v7_9_ih_doorbell_range()
289 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); in nbio_v7_9_ih_doorbell_range()
292 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); in nbio_v7_9_ih_doorbell_range()
296 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); in nbio_v7_9_ih_doorbell_range()
299 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); in nbio_v7_9_ih_doorbell_range()
302 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); in nbio_v7_9_ih_doorbell_range()
303 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); in nbio_v7_9_ih_doorbell_range()
327 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_9_ih_control()
328 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); in nbio_v7_9_ih_control()
329 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi in nbio_v7_9_ih_control()
333 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in nbio_v7_9_ih_control()
336 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in nbio_v7_9_ih_control()
337 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); in nbio_v7_9_ih_control()
342 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v7_9_get_hdp_flush_req_offset()
347 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); in nbio_v7_9_get_hdp_flush_done_offset()
352 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); in nbio_v7_9_get_pcie_index_offset()
357 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); in nbio_v7_9_get_pcie_data_offset()
362 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); in nbio_v7_9_get_pcie_index_hi_offset()
389 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, in nbio_v7_9_enable_doorbell_interrupt()
390 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); in nbio_v7_9_enable_doorbell_interrupt()
397 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); in nbio_v7_9_get_compute_partition_mode()
409 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); in nbio_v7_9_get_memory_partition_mode()
414 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); in nbio_v7_9_get_memory_partition_mode()
425 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, in nbio_v7_9_init_registers()
426 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
428 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); in nbio_v7_9_init_registers()
461 return 0; in nbio_v7_9_get_pcie_replay_count()
465 nak_r = val & 0xFFFF; in nbio_v7_9_get_pcie_replay_count()
472 #define MMIO_REG_HOLE_OFFSET 0x1A000
482 NBIO, 0, in nbio_v7_9_set_reg_remap()
485 adev->rmmio_remap.bus_addr = 0; in nbio_v7_9_set_reg_remap()
531 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); in nbio_v7_9_handle_ras_controller_intr_no_bifring()
539 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); in nbio_v7_9_handle_ras_controller_intr_no_bifring()
577 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); in nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring()
586 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); in nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring()
599 return 0; in nbio_v7_9_set_ras_controller_irq_state()
611 return 0; in nbio_v7_9_process_ras_controller_irq()
621 return 0; in nbio_v7_9_set_ras_err_event_athub_irq_state()
633 return 0; in nbio_v7_9_process_err_event_athub_irq()