Lines Matching +full:0 +full:x000000ff

26 #define SDMA_OP_NOP  0
44 #define SDMA_SUBOP_TIMESTAMP_SET  0
47 #define SDMA_SUBOP_COPY_LINEAR  0
60 #define SDMA_SUBOP_WRITE_LINEAR  0
63 #define SDMA_SUBOP_PTEPDE_GEN  0
73 #define SDMA_OP_AQL_COPY  0
74 #define SDMA_OP_AQL_BARRIER_OR  0
77 #define SDMA_GCR_SEQ(x)			(((x) & 0x3) << 16)
81 #define SDMA_GCR_GL2_RANGE(x)		(((x) & 0x3) << 11)
89 #define SDMA_GCR_GL1_RANGE(x)		(((x) & 0x3) << 2)
90 #define SDMA_GCR_GLI_INV(x)		(((x) & 0x3) << 0)
93 #define SDMA_PKT_HEADER_op_offset 0
94 #define SDMA_PKT_HEADER_op_mask   0x000000FF
95 #define SDMA_PKT_HEADER_op_shift  0
99 #define SDMA_PKT_HEADER_sub_op_offset 0
100 #define SDMA_PKT_HEADER_sub_op_mask   0x000000FF
110 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
111 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask   0x000000FF
112 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift  0
116 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
117 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask   0x000000FF
122 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0
123 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask   0x00000001
128 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0
129 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask   0x00000001
134 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0
135 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask   0x00000001
140 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
141 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask   0x00000001
148 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask   0x003FFFFF
149 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift  0
155 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
161 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
168 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
169 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
175 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
176 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
182 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
183 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
189 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
190 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
200 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0
201 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask   0x000000FF
202 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift  0
206 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0
207 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask   0x000000FF
214 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask   0x003FFFFF
215 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift  0
221 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask   0x00000003
227 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask   0x00000001
233 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask   0x00000003
239 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask   0x00000001
246 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
247 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
253 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
254 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
260 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
261 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
267 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
268 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
278 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0
279 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask   0x000000FF
280 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift  0
284 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0
285 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask   0x000000FF
290 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0
291 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask   0x00000001
296 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0
297 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask   0x00000001
304 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask   0x003FFFFF
305 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift  0
311 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask   0x00000007
317 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask   0x00000003
323 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask   0x00000007
329 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask   0x00000003
335 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask   0x00000003
341 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask   0x00000001
347 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask   0x00000001
353 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask   0x00000001
359 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask   0x00000001
365 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask   0x00000003
371 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask   0x00000001
377 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask   0x00000001
383 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask   0x00000001
390 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
391 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift  0
397 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
398 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift  0
404 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
405 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift  0
411 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
412 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift  0
422 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0
423 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask   0x000000FF
424 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift  0
428 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0
429 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask   0x000000FF
434 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0
435 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask   0x00000001
442 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask   0x003FFFFF
443 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift  0
449 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask   0x00000007
455 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask   0x00000003
461 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask   0x00000007
467 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask   0x00000003
473 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask   0x00000003
479 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask   0x00000001
485 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask   0x00000001
491 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask   0x00000001
497 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask   0x00000001
503 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask   0x00000001
509 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask   0x00000003
515 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask   0x00000001
521 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask   0x00000001
527 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask   0x00000001
533 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask   0x00000001
540 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
541 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
547 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
548 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
554 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
555 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
561 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
562 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
572 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
573 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask   0x000000FF
574 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift  0
578 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
579 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask   0x000000FF
584 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0
585 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask   0x00000001
590 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0
591 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask   0x00000001
596 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
597 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask   0x00000001
604 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask   0x003FFFFF
605 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift  0
611 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask   0x00000003
617 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask   0x00000003
623 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask   0x00000003
630 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
631 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
637 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
638 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
644 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask   0xFFFFFFFF
645 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift  0
651 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask   0xFFFFFFFF
652 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift  0
658 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask   0xFFFFFFFF
659 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift  0
665 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask   0xFFFFFFFF
666 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift  0
676 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
677 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask   0x000000FF
678 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift  0
682 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
683 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask   0x000000FF
688 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0
689 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask   0x00000001
694 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
695 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask   0x00000007
702 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
703 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift  0
709 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
710 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift  0
716 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask   0x00003FFF
717 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift  0
722 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask   0x00003FFF
729 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask   0x00001FFF
730 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift  0
735 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask   0x0007FFFF
742 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask   0x0FFFFFFF
743 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift  0
749 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
750 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift  0
756 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
757 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift  0
763 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask   0x00003FFF
764 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift  0
769 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask   0x00003FFF
776 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask   0x00001FFF
777 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift  0
782 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask   0x0007FFFF
789 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
790 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift  0
796 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask   0x00003FFF
797 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift  0
802 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask   0x00003FFF
809 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask   0x00001FFF
810 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift  0
815 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask   0x00000003
821 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask   0x00000003
832 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0
833 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask   0x000000FF
834 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift  0
838 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0
839 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask   0x000000FF
844 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0
845 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask   0x00000007
852 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
853 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
859 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
860 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
866 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask   0x00003FFF
867 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift  0
872 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask   0x00003FFF
879 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask   0x000007FF
880 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift  0
885 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask   0x00003FFF
892 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask   0x0FFFFFFF
893 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift  0
899 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
900 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
906 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
907 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
913 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask   0x00003FFF
914 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift  0
919 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask   0x00003FFF
926 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask   0x000007FF
927 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift  0
932 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask   0x00003FFF
939 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
940 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift  0
946 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask   0x00003FFF
947 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift  0
952 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask   0x00003FFF
959 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask   0x000007FF
960 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift  0
965 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask   0x00000003
971 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask   0x00000001
977 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask   0x00000003
983 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask   0x00000001
994 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
995 #define SDMA_PKT_COPY_TILED_HEADER_op_mask   0x000000FF
996 #define SDMA_PKT_COPY_TILED_HEADER_op_shift  0
1000 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
1001 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask   0x000000FF
1006 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0
1007 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask   0x00000001
1012 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0
1013 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask   0x00000001
1018 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
1019 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask   0x00000001
1026 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
1027 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift  0
1033 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
1034 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift  0
1040 #define SDMA_PKT_COPY_TILED_DW_3_width_mask   0x00003FFF
1041 #define SDMA_PKT_COPY_TILED_DW_3_width_shift  0
1047 #define SDMA_PKT_COPY_TILED_DW_4_height_mask   0x00003FFF
1048 #define SDMA_PKT_COPY_TILED_DW_4_height_shift  0
1053 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask   0x00001FFF
1060 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask   0x00000007
1061 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift  0
1066 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask   0x0000001F
1072 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask   0x00000003
1078 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask   0x0000000F
1085 #define SDMA_PKT_COPY_TILED_DW_6_x_mask   0x00003FFF
1086 #define SDMA_PKT_COPY_TILED_DW_6_x_shift  0
1091 #define SDMA_PKT_COPY_TILED_DW_6_y_mask   0x00003FFF
1098 #define SDMA_PKT_COPY_TILED_DW_7_z_mask   0x00001FFF
1099 #define SDMA_PKT_COPY_TILED_DW_7_z_shift  0
1104 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask   0x00000003
1110 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask   0x00000001
1116 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask   0x00000003
1123 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1124 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1130 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1131 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1137 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1138 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift  0
1144 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask   0xFFFFFFFF
1145 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift  0
1151 #define SDMA_PKT_COPY_TILED_COUNT_count_mask   0x003FFFFF
1152 #define SDMA_PKT_COPY_TILED_COUNT_count_shift  0
1162 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0
1163 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask   0x000000FF
1164 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift  0
1168 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0
1169 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask   0x000000FF
1174 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0
1175 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask   0x00000001
1182 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
1183 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift  0
1189 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
1190 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift  0
1196 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask   0x00003FFF
1197 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift  0
1203 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask   0x00003FFF
1204 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift  0
1209 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask   0x000007FF
1216 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask   0x00000007
1217 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift  0
1222 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask   0x0000000F
1228 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask   0x00000007
1234 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask   0x00000007
1240 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask   0x00000003
1246 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask   0x00000003
1252 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask   0x00000003
1258 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask   0x00000003
1264 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask   0x0000001F
1271 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask   0x00003FFF
1272 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift  0
1277 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask   0x00003FFF
1284 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask   0x000007FF
1285 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift  0
1290 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask   0x00000003
1296 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask   0x00000003
1303 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1304 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1310 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1311 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1317 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1318 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift  0
1324 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask   0x000FFFFF
1335 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
1336 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask   0x000000FF
1337 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift  0
1341 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
1342 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask   0x000000FF
1347 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0
1348 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask   0x00000001
1353 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0
1354 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask   0x00000001
1359 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
1360 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask   0x00000001
1365 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
1366 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask   0x00000001
1373 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask   0xFFFFFFFF
1374 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift  0
1380 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask   0xFFFFFFFF
1381 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift  0
1387 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask   0xFFFFFFFF
1388 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift  0
1394 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask   0xFFFFFFFF
1395 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift  0
1401 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask   0x00003FFF
1402 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift  0
1408 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask   0x00003FFF
1409 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift  0
1414 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask   0x00001FFF
1421 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask   0x00000007
1422 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift  0
1427 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask   0x0000001F
1433 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask   0x00000003
1439 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask   0x0000000F
1446 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask   0x00003FFF
1447 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift  0
1452 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask   0x00003FFF
1459 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask   0x00001FFF
1460 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift  0
1466 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask   0x00000003
1472 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask   0x00000003
1478 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask   0x00000003
1485 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
1486 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
1492 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
1493 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
1499 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
1500 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift  0
1506 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask   0xFFFFFFFF
1507 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift  0
1513 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask   0x003FFFFF
1514 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift  0
1524 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
1525 #define SDMA_PKT_COPY_T2T_HEADER_op_mask   0x000000FF
1526 #define SDMA_PKT_COPY_T2T_HEADER_op_shift  0
1530 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
1531 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask   0x000000FF
1536 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0
1537 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask   0x00000001
1542 #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0
1543 #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask   0x00000001
1548 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0
1549 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask   0x00000001
1556 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
1557 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift  0
1563 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
1564 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift  0
1570 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask   0x00003FFF
1571 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift  0
1576 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask   0x00003FFF
1583 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask   0x00001FFF
1584 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift  0
1589 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask   0x00003FFF
1596 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask   0x00003FFF
1597 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift  0
1602 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask   0x00001FFF
1609 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask   0x00000007
1610 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift  0
1615 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask   0x0000001F
1621 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask   0x00000003
1627 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask   0x0000000F
1633 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask   0x0000000F
1640 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
1641 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift  0
1647 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
1648 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift  0
1654 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask   0x00003FFF
1655 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift  0
1660 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask   0x00003FFF
1667 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask   0x00001FFF
1668 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift  0
1673 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask   0x00003FFF
1680 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask   0x00003FFF
1681 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift  0
1686 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask   0x00001FFF
1693 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask   0x00000007
1694 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift  0
1699 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask   0x0000001F
1705 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask   0x00000003
1711 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask   0x0000000F
1717 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask   0x0000000F
1724 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask   0x00003FFF
1725 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift  0
1730 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask   0x00003FFF
1737 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask   0x00001FFF
1738 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift  0
1743 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask   0x00000003
1749 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask   0x00000003
1756 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask   0xFFFFFFFF
1757 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift  0
1763 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask   0xFFFFFFFF
1764 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift  0
1770 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask   0x0000007F
1771 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift  0
1776 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask   0x00000001
1782 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask   0x00000001
1788 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask   0x00000007
1794 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask   0x00000003
1800 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask   0x00000003
1806 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask   0x00000003
1812 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask   0x00000001
1818 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask   0x00000001
1829 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0
1830 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask   0x000000FF
1831 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift  0
1835 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0
1836 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask   0x000000FF
1843 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
1844 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift  0
1850 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
1851 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift  0
1857 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask   0x00003FFF
1858 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift  0
1863 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask   0x00003FFF
1870 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask   0x000007FF
1871 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift  0
1876 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask   0x00003FFF
1883 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask   0x00003FFF
1884 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift  0
1889 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask   0x000007FF
1896 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask   0x00000007
1897 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift  0
1902 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask   0x0000000F
1908 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask   0x00000007
1914 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask   0x00000007
1920 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask   0x00000003
1926 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask   0x00000003
1932 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask   0x00000003
1938 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask   0x00000003
1944 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask   0x0000001F
1951 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
1952 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
1958 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
1959 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
1965 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask   0x00003FFF
1966 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift  0
1971 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask   0x00003FFF
1978 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask   0x000007FF
1979 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift  0
1984 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask   0x00003FFF
1991 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask   0x00003FFF
1992 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift  0
1997 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask   0x00000FFF
2004 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask   0x00000007
2005 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift  0
2010 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask   0x0000000F
2016 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask   0x00000007
2022 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask   0x00000007
2028 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask   0x00000003
2034 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask   0x00000003
2040 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask   0x00000003
2046 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask   0x00000003
2052 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask   0x0000001F
2059 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask   0x00003FFF
2060 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift  0
2065 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask   0x00003FFF
2072 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask   0x000007FF
2073 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift  0
2078 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask   0x00000003
2084 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask   0x00000003
2095 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
2096 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask   0x000000FF
2097 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift  0
2101 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
2102 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask   0x000000FF
2107 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0
2108 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask   0x00000001
2113 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0
2114 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask   0x00000001
2119 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
2120 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask   0x00000001
2127 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
2128 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift  0
2134 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
2135 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift  0
2141 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask   0x00003FFF
2142 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift  0
2147 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask   0x00003FFF
2154 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask   0x00001FFF
2155 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift  0
2160 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask   0x00003FFF
2167 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask   0x00003FFF
2168 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift  0
2173 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask   0x00001FFF
2180 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask   0x00000007
2181 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift  0
2186 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask   0x0000001F
2192 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask   0x00000003
2198 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask   0x0000000F
2204 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask   0x0000000F
2211 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
2212 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
2218 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
2219 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
2225 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask   0x00003FFF
2226 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift  0
2231 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask   0x00003FFF
2238 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask   0x00001FFF
2239 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift  0
2244 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask   0x00003FFF
2251 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
2252 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift  0
2258 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask   0x00003FFF
2259 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift  0
2264 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask   0x00003FFF
2271 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask   0x00001FFF
2272 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift  0
2277 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask   0x00000003
2283 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask   0x00000003
2290 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask   0xFFFFFFFF
2291 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift  0
2297 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask   0xFFFFFFFF
2298 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift  0
2304 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask   0x0000007F
2305 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift  0
2310 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask   0x00000001
2316 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask   0x00000001
2322 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask   0x00000007
2328 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask   0x00000003
2334 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask   0x00000003
2340 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask   0x00000003
2346 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask   0x00000001
2352 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask   0x00000001
2363 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0
2364 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask   0x000000FF
2365 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift  0
2369 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0
2370 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask   0x000000FF
2375 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0
2376 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask   0x00000001
2383 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
2384 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift  0
2390 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
2391 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift  0
2397 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask   0x00003FFF
2398 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift  0
2403 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask   0x00003FFF
2410 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask   0x000007FF
2411 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift  0
2416 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask   0x00003FFF
2423 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask   0x00003FFF
2424 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift  0
2429 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask   0x000007FF
2436 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask   0x00000007
2437 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift  0
2442 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask   0x0000000F
2448 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask   0x00000007
2454 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask   0x00000007
2460 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask   0x00000003
2466 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask   0x00000003
2472 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask   0x00000003
2478 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask   0x00000003
2484 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask   0x0000001F
2491 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
2492 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
2498 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
2499 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
2505 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask   0x00003FFF
2506 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift  0
2511 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask   0x00003FFF
2518 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask   0x000007FF
2519 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift  0
2524 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask   0x00003FFF
2531 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
2532 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift  0
2538 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask   0x00003FFF
2539 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift  0
2544 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask   0x00003FFF
2551 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask   0x000007FF
2552 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift  0
2557 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask   0x00000003
2563 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask   0x00000003
2574 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
2575 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask   0x000000FF
2576 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift  0
2580 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
2581 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask   0x000000FF
2586 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0
2587 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask   0x00000001
2592 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
2593 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask   0x00000001
2600 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask   0xFFFFFFFF
2601 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift  0
2607 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask   0xFFFFFFFF
2608 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift  0
2614 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask   0xFFFFFFFF
2615 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift  0
2621 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask   0xFFFFFFFF
2622 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift  0
2628 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask   0x000007FF
2629 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift  0
2634 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask   0x00000003
2640 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask   0x00000003
2647 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
2648 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
2654 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
2655 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
2665 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
2666 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask   0x000000FF
2667 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift  0
2671 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
2672 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask   0x000000FF
2677 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0
2678 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask   0x00000001
2683 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0
2684 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask   0x00000001
2691 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
2692 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift  0
2698 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
2699 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift  0
2705 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask   0x000FFFFF
2706 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift  0
2711 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask   0x00000003
2718 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask   0xFFFFFFFF
2719 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift  0
2729 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
2730 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask   0x000000FF
2731 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift  0
2735 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
2736 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask   0x000000FF
2741 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0
2742 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask   0x00000001
2747 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0
2748 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask   0x00000001
2755 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
2756 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift  0
2762 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
2763 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift  0
2769 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask   0x00003FFF
2770 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift  0
2776 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask   0x00003FFF
2777 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift  0
2782 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask   0x00001FFF
2789 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask   0x00000007
2790 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift  0
2795 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask   0x0000001F
2801 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask   0x00000003
2807 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask   0x0000000F
2814 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask   0x00003FFF
2815 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift  0
2820 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask   0x00003FFF
2827 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask   0x00001FFF
2828 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift  0
2833 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask   0x00000003
2840 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask   0x000FFFFF
2841 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift  0
2847 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask   0xFFFFFFFF
2848 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift  0
2858 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0
2859 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask   0x000000FF
2860 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift  0
2864 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0
2865 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask   0x000000FF
2872 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
2873 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift  0
2879 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
2880 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift  0
2886 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask   0x00003FFF
2887 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift  0
2893 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask   0x00003FFF
2894 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift  0
2899 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask   0x000007FF
2906 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask   0x00000007
2907 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift  0
2912 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask   0x0000000F
2918 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask   0x00000007
2924 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask   0x00000007
2930 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask   0x00000003
2936 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask   0x00000003
2942 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask   0x00000003
2948 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask   0x00000003
2954 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask   0x0000001F
2961 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask   0x00003FFF
2962 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift  0
2967 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask   0x00003FFF
2974 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask   0x000007FF
2975 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift  0
2980 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask   0x00000003
2987 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask   0x000FFFFF
2994 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask   0xFFFFFFFF
2995 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift  0
3005 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0
3006 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask   0x000000FF
3007 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift  0
3011 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0
3012 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask   0x000000FF
3017 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0
3018 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask   0x00000001
3023 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0
3024 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask   0x00000001
3031 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
3032 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift  0
3038 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
3039 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift  0
3045 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3046 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift  0
3052 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3053 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift  0
3059 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
3060 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift  0
3066 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
3067 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift  0
3073 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask   0x0007FFFF
3074 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift  0
3084 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0
3085 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask   0x000000FF
3086 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift  0
3090 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0
3091 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask   0x000000FF
3096 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0
3097 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask   0x00000003
3102 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0
3103 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask   0x00000001
3108 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0
3109 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask   0x00000001
3116 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
3117 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift  0
3123 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
3124 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift  0
3130 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3131 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift  0
3137 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3138 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift  0
3144 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask   0x000000FF
3145 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift  0
3150 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask   0x000000FF
3157 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask   0x0001FFFF
3158 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift  0
3168 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0
3169 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask   0x000000FF
3170 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift  0
3174 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0
3175 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask   0x000000FF
3180 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0
3181 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask   0x00000007
3186 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0
3187 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask   0x00000001
3192 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0
3193 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask   0x00000001
3198 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0
3199 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask   0x00000001
3204 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0
3205 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask   0x00000001
3210 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0
3211 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask   0x00000003
3218 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3219 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift  0
3225 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3226 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift  0
3232 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask   0xFFFFFFFF
3233 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift  0
3239 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask   0xFFFFFFFF
3240 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift  0
3246 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask   0xFFFFFFFF
3247 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift  0
3253 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask   0xFFFFFFFF
3254 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift  0
3264 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
3265 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask   0x000000FF
3266 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift  0
3270 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
3271 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask   0x000000FF
3278 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3279 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift  0
3285 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3286 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift  0
3292 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
3293 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift  0
3299 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
3300 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift  0
3306 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask   0xFFFFFFFF
3307 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift  0
3313 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask   0xFFFFFFFF
3314 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift  0
3320 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask   0xFFFFFFFF
3321 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift  0
3327 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask   0xFFFFFFFF
3328 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift  0
3334 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask   0x0007FFFF
3335 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift  0
3345 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0
3346 #define SDMA_PKT_INDIRECT_HEADER_op_mask   0x000000FF
3347 #define SDMA_PKT_INDIRECT_HEADER_op_shift  0
3351 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
3352 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask   0x000000FF
3357 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
3358 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask   0x0000000F
3363 #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0
3364 #define SDMA_PKT_INDIRECT_HEADER_priv_mask   0x00000001
3371 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask   0xFFFFFFFF
3372 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift  0
3378 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask   0xFFFFFFFF
3379 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift  0
3385 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask   0x000FFFFF
3386 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift  0
3392 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask   0xFFFFFFFF
3393 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift  0
3399 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask   0xFFFFFFFF
3400 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift  0
3410 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
3411 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask   0x000000FF
3412 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift  0
3416 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
3417 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask   0x000000FF
3422 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
3423 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask   0x00000001
3428 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
3429 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask   0x00000001
3434 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
3435 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask   0x00000001
3442 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3443 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift  0
3449 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3450 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift  0
3460 #define SDMA_PKT_FENCE_HEADER_op_offset 0
3461 #define SDMA_PKT_FENCE_HEADER_op_mask   0x000000FF
3462 #define SDMA_PKT_FENCE_HEADER_op_shift  0
3466 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
3467 #define SDMA_PKT_FENCE_HEADER_sub_op_mask   0x000000FF
3472 #define SDMA_PKT_FENCE_HEADER_mtype_offset 0
3473 #define SDMA_PKT_FENCE_HEADER_mtype_mask   0x00000007
3478 #define SDMA_PKT_FENCE_HEADER_gcc_offset 0
3479 #define SDMA_PKT_FENCE_HEADER_gcc_mask   0x00000001
3484 #define SDMA_PKT_FENCE_HEADER_sys_offset 0
3485 #define SDMA_PKT_FENCE_HEADER_sys_mask   0x00000001
3490 #define SDMA_PKT_FENCE_HEADER_snp_offset 0
3491 #define SDMA_PKT_FENCE_HEADER_snp_mask   0x00000001
3496 #define SDMA_PKT_FENCE_HEADER_gpa_offset 0
3497 #define SDMA_PKT_FENCE_HEADER_gpa_mask   0x00000001
3502 #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0
3503 #define SDMA_PKT_FENCE_HEADER_l2_policy_mask   0x00000003
3510 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3511 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift  0
3517 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3518 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift  0
3524 #define SDMA_PKT_FENCE_DATA_data_mask   0xFFFFFFFF
3525 #define SDMA_PKT_FENCE_DATA_data_shift  0
3535 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
3536 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask   0x000000FF
3537 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift  0
3541 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
3542 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask   0x000000FF
3547 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
3548 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask   0x0000000F
3555 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask   0x0003FFFF
3556 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift  0
3561 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask   0x00000FFF
3568 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask   0xFFFFFFFF
3569 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift  0
3579 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
3580 #define SDMA_PKT_PRE_EXE_HEADER_op_mask   0x000000FF
3581 #define SDMA_PKT_PRE_EXE_HEADER_op_shift  0
3585 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
3586 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask   0x000000FF
3591 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
3592 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask   0x000000FF
3599 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
3600 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift  0
3610 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0
3611 #define SDMA_PKT_COND_EXE_HEADER_op_mask   0x000000FF
3612 #define SDMA_PKT_COND_EXE_HEADER_op_shift  0
3616 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
3617 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask   0x000000FF
3624 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3625 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift  0
3631 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3632 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift  0
3638 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask   0xFFFFFFFF
3639 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift  0
3645 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
3646 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift  0
3656 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
3657 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask   0x000000FF
3658 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift  0
3662 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
3663 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask   0x000000FF
3668 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
3669 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask   0x00000003
3674 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
3675 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask   0x00000003
3682 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3683 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift  0
3689 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3690 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift  0
3696 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask   0xFFFFFFFF
3697 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift  0
3703 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask   0x003FFFFF
3704 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift  0
3714 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0
3715 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask   0x000000FF
3716 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift  0
3720 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0
3721 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask   0x000000FF
3726 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0
3727 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask   0x00000001
3734 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask   0xFFFFFFFF
3735 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift  0
3741 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask   0xFFFFFFFF
3742 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift  0
3748 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
3749 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift  0
3755 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
3756 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift  0
3762 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask   0x03FFFFFF
3763 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift  0
3773 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
3774 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask   0x000000FF
3775 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift  0
3779 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
3780 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask   0x000000FF
3785 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
3786 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask   0x00000001
3791 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
3792 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask   0x00000007
3797 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
3798 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask   0x00000001
3805 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3806 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift  0
3812 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3813 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift  0
3819 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask   0xFFFFFFFF
3820 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift  0
3826 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask   0xFFFFFFFF
3827 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift  0
3833 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask   0x0000FFFF
3834 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift  0
3839 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask   0x00000FFF
3850 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0
3851 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask   0x000000FF
3852 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift  0
3856 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0
3857 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask   0x000000FF
3864 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask   0x3FFFFFFF
3871 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3872 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift  0
3878 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3879 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift  0
3889 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0
3890 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask   0x000000FF
3891 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift  0
3895 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0
3896 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask   0x000000FF
3901 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0
3902 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask   0x00000003
3909 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
3910 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift  0
3916 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
3917 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift  0
3923 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask   0x0FFFFFFF
3930 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask   0xFFFFFFFF
3931 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift  0
3941 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0
3942 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask   0x000000FF
3943 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift  0
3947 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0
3948 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask   0x000000FF
3953 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0
3954 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask   0x00000001
3961 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask   0xFFFFFFFF
3962 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift  0
3968 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask   0xFFFFFFFF
3969 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift  0
3975 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask   0xFFFFFFFF
3976 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift  0
3982 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask   0xFFFFFFFF
3983 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift  0
3989 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask   0xFFFFFFFF
3990 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift  0
3996 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask   0xFFFFFFFF
3997 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift  0
4003 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask   0xFFFFFFFF
4004 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift  0
4010 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask   0xFFFFFFFF
4011 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift  0
4017 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask   0xFFFFFFFF
4018 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift  0
4024 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask   0xFFFFFFFF
4025 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift  0
4031 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask   0xFFFFFFFF
4032 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift  0
4038 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask   0xFFFFFFFF
4039 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift  0
4049 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0
4050 #define SDMA_PKT_ATOMIC_HEADER_op_mask   0x000000FF
4051 #define SDMA_PKT_ATOMIC_HEADER_op_shift  0
4055 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
4056 #define SDMA_PKT_ATOMIC_HEADER_loop_mask   0x00000001
4061 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0
4062 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask   0x00000001
4067 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
4068 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask   0x0000007F
4075 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
4076 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift  0
4082 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
4083 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift  0
4089 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask   0xFFFFFFFF
4090 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift  0
4096 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask   0xFFFFFFFF
4097 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift  0
4103 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask   0xFFFFFFFF
4104 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift  0
4110 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask   0xFFFFFFFF
4111 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift  0
4117 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask   0x00001FFF
4118 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift  0
4128 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
4129 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask   0x000000FF
4130 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift  0
4134 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
4135 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask   0x000000FF
4142 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask   0xFFFFFFFF
4143 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift  0
4149 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask   0xFFFFFFFF
4150 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift  0
4160 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
4161 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask   0x000000FF
4162 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift  0
4166 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
4167 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask   0x000000FF
4174 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
4181 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
4182 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift  0
4192 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
4193 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask   0x000000FF
4194 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift  0
4198 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
4199 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask   0x000000FF
4206 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
4213 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
4214 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift  0
4224 #define SDMA_PKT_TRAP_HEADER_op_offset 0
4225 #define SDMA_PKT_TRAP_HEADER_op_mask   0x000000FF
4226 #define SDMA_PKT_TRAP_HEADER_op_shift  0
4230 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
4231 #define SDMA_PKT_TRAP_HEADER_sub_op_mask   0x000000FF
4238 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
4239 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift  0
4249 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0
4250 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask   0x000000FF
4251 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift  0
4255 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0
4256 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask   0x000000FF
4263 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
4264 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift  0
4274 #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0
4275 #define SDMA_PKT_GPUVM_INV_HEADER_op_mask   0x000000FF
4276 #define SDMA_PKT_GPUVM_INV_HEADER_op_shift  0
4280 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0
4281 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask   0x000000FF
4288 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask   0x0000FFFF
4289 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift  0
4294 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask   0x00000007
4300 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask   0x00000001
4306 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask   0x00000001
4312 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask   0x00000001
4318 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask   0x00000001
4324 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask   0x00000001
4330 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask   0x00000001
4336 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask   0x00000001
4342 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask   0x00000001
4349 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask   0x00000001
4350 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift  0
4355 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask   0x7FFFFFFF
4362 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask   0x0000003F
4363 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift  0
4373 #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0
4374 #define SDMA_PKT_GCR_REQ_HEADER_op_mask   0x000000FF
4375 #define SDMA_PKT_GCR_REQ_HEADER_op_shift  0
4379 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0
4380 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask   0x000000FF
4387 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask   0x01FFFFFF
4394 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask   0x0000FFFF
4395 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift  0
4400 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask   0x0000FFFF
4407 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask   0x00000007
4408 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift  0
4413 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask   0x01FFFFFF
4420 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask   0x0000FFFF
4421 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift  0
4426 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask   0x0000000F
4437 #define SDMA_PKT_NOP_HEADER_op_offset 0
4438 #define SDMA_PKT_NOP_HEADER_op_mask   0x000000FF
4439 #define SDMA_PKT_NOP_HEADER_op_shift  0
4443 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0
4444 #define SDMA_PKT_NOP_HEADER_sub_op_mask   0x000000FF
4449 #define SDMA_PKT_NOP_HEADER_count_offset 0
4450 #define SDMA_PKT_NOP_HEADER_count_mask   0x00003FFF
4457 #define SDMA_PKT_NOP_DATA0_data0_mask   0xFFFFFFFF
4458 #define SDMA_PKT_NOP_DATA0_data0_shift  0
4468 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0
4469 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask   0x000000FF
4470 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift  0
4474 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0
4475 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask   0x00000001
4480 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0
4481 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask   0x00000003
4486 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0
4487 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask   0x00000003
4492 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0
4493 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask   0x00000007
4498 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0
4499 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask   0x0000000F
4504 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0
4505 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask   0x00000007
4516 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0
4517 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask   0x000000FF
4518 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift  0
4522 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0
4523 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask   0x00000001
4528 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0
4529 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask   0x00000003
4534 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0
4535 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask   0x00000003
4540 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0
4541 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask   0x00000007
4546 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0
4547 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask   0x0000000F
4552 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0
4553 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask   0x00000007
4560 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask   0xFFFFFFFF
4561 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift  0
4567 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask   0xFFFFFFFF
4568 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift  0
4574 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask   0xFFFFFFFF
4575 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift  0
4581 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask   0x003FFFFF
4582 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift  0
4588 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
4594 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
4601 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
4602 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
4608 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
4609 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
4615 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
4616 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
4622 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
4623 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
4629 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask   0xFFFFFFFF
4630 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift  0
4636 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask   0xFFFFFFFF
4637 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift  0
4643 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask   0xFFFFFFFF
4644 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift  0
4650 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask   0xFFFFFFFF
4651 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift  0
4657 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask   0xFFFFFFFF
4658 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift  0
4664 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask   0xFFFFFFFF
4665 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift  0
4675 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0
4676 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask   0x000000FF
4677 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift  0
4681 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0
4682 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask   0x00000001
4687 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0
4688 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask   0x00000003
4693 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0
4694 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask   0x00000003
4699 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0
4700 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask   0x00000007
4705 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0
4706 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask   0x0000000F
4711 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0
4712 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask   0x00000007
4719 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask   0xFFFFFFFF
4720 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift  0
4726 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask   0xFFFFFFFF
4727 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift  0
4733 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask   0xFFFFFFFF
4734 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift  0
4740 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask   0xFFFFFFFF
4741 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift  0
4747 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask   0xFFFFFFFF
4748 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift  0
4754 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask   0xFFFFFFFF
4755 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift  0
4761 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask   0xFFFFFFFF
4762 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift  0
4768 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask   0xFFFFFFFF
4769 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift  0
4775 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask   0xFFFFFFFF
4776 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift  0
4782 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask   0xFFFFFFFF
4783 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift  0
4789 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask   0xFFFFFFFF
4790 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift  0
4796 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask   0xFFFFFFFF
4797 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift  0
4803 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask   0xFFFFFFFF
4804 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift  0
4810 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask   0xFFFFFFFF
4811 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift  0
4817 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask   0xFFFFFFFF
4818 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift  0