Lines Matching refs:IH_RB_CNTL
162 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in navi10_ih_toggle_ring_interrupts()
163 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); in navi10_ih_toggle_ring_interrupts()
166 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in navi10_ih_toggle_ring_interrupts()
217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
223 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in navi10_ih_rb_cntl()
230 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in navi10_ih_rb_cntl()
231 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in navi10_ih_rb_cntl()
278 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); in navi10_ih_enable_ring()
280 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); in navi10_ih_enable_ring()
443 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in navi10_ih_get_wptr()
449 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); in navi10_ih_get_wptr()