Lines Matching full:jpeg
74 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
77 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
86 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
95 * jpeg_v4_0_5_sw_init - sw init for JPEG block
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
108 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
111 /* JPEG TRAP */ in jpeg_v4_0_5_sw_init()
113 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
117 /* JPEG DJPEG POISON EVENT */ in jpeg_v4_0_5_sw_init()
119 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
123 /* JPEG EJPEG POISON EVENT */ in jpeg_v4_0_5_sw_init()
125 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
139 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
142 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_sw_init()
147 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, in jpeg_v4_0_5_sw_init()
152 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v4_0_5_sw_init()
153 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH); in jpeg_v4_0_5_sw_init()
160 * jpeg_v4_0_5_sw_fini - sw fini for JPEG block
164 * JPEG suspend and free up sw allocation
181 * jpeg_v4_0_5_hw_init - start and test JPEG block
197 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_hw_init()
198 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_hw_init()
201 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_hw_init()
215 * Stop the JPEG block, mark ring as not ready any more
224 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_hw_fini()
225 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_hw_fini()
229 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v4_0_5_hw_fini()
230 RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS)) in jpeg_v4_0_5_hw_fini()
238 * jpeg_v4_0_5_suspend - suspend JPEG block
242 * HW fini and suspend JPEG block
259 * jpeg_v4_0_5_resume - resume JPEG block
263 * Resume firmware and hw init JPEG block
283 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_disable_clock_gating()
293 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_disable_clock_gating()
295 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); in jpeg_v4_0_5_disable_clock_gating()
300 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data); in jpeg_v4_0_5_disable_clock_gating()
307 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_enable_clock_gating()
317 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_enable_clock_gating()
319 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); in jpeg_v4_0_5_enable_clock_gating()
324 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data); in jpeg_v4_0_5_enable_clock_gating()
349 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_disable_static_power_gating()
351 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_disable_static_power_gating()
356 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_5_disable_static_power_gating()
359 /* keep the JPEG in static PG mode */ in jpeg_v4_0_5_disable_static_power_gating()
360 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_5_disable_static_power_gating()
369 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), in jpeg_v4_0_5_enable_static_power_gating()
374 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_enable_static_power_gating()
376 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_enable_static_power_gating()
385 * jpeg_v4_0_5_start_dpg_mode - Jpeg start with dpg mode
391 * Start JPEG block with dpg mode
395 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
399 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
402 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_start_dpg_mode()
405 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_start_dpg_mode()
407 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
412 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
414 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_start_dpg_mode()
417 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v4_0_5_start_dpg_mode()
418 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v4_0_5_start_dpg_mode()
435 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v4_0_5_start_dpg_mode()
436 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v4_0_5_start_dpg_mode()
437 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v4_0_5_start_dpg_mode()
439 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v4_0_5_start_dpg_mode()
441 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v4_0_5_start_dpg_mode()
442 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_5_start_dpg_mode()
443 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v4_0_5_start_dpg_mode()
444 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_5_start_dpg_mode()
445 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start_dpg_mode()
449 * jpeg_v4_0_5_stop_dpg_mode - Jpeg stop with dpg mode
454 * Stop JPEG block with dpg mode
460 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_stop_dpg_mode()
462 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_stop_dpg_mode()
467 * jpeg_v4_0_5_start - start JPEG block
471 * Setup and start the JPEG block
481 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_start()
482 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_start()
485 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_start()
495 jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram); in jpeg_v4_0_5_start()
504 /* JPEG disable CGC */ in jpeg_v4_0_5_start()
508 WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v4_0_5_start()
512 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0, in jpeg_v4_0_5_start()
516 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN), in jpeg_v4_0_5_start()
520 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v4_0_5_start()
521 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v4_0_5_start()
522 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v4_0_5_start()
524 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v4_0_5_start()
526 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_RPTR, 0); in jpeg_v4_0_5_start()
527 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_5_start()
528 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v4_0_5_start()
529 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_5_start()
530 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start()
537 * jpeg_v4_0_5_stop - stop JPEG block
541 * stop the JPEG block
547 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_stop()
548 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_stop()
557 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), in jpeg_v4_0_5_stop()
585 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_RPTR); in jpeg_v4_0_5_dec_ring_get_rptr()
602 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_dec_ring_get_wptr()
620 WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v4_0_5_dec_ring_set_wptr()
629 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_is_idle()
630 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_is_idle()
633 ret &= (((RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS) & in jpeg_v4_0_5_is_idle()
645 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_wait_for_idle()
646 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_wait_for_idle()
649 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS, in jpeg_v4_0_5_wait_for_idle()
664 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_set_clockgating_state()
665 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_set_clockgating_state()
688 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; in jpeg_v4_0_5_set_powergating_state()
692 if (state == adev->jpeg.cur_state) in jpeg_v4_0_5_set_powergating_state()
701 adev->jpeg.cur_state = state; in jpeg_v4_0_5_set_powergating_state()
712 DRM_DEBUG("IH: JPEG TRAP\n"); in jpeg_v4_0_5_process_interrupt()
728 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec); in jpeg_v4_0_5_process_interrupt()
799 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_set_dec_ring_funcs()
800 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_set_dec_ring_funcs()
803 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs; in jpeg_v4_0_5_set_dec_ring_funcs()
804 adev->jpeg.inst[i].ring_dec->me = i; in jpeg_v4_0_5_set_dec_ring_funcs()
816 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_set_irq_funcs()
817 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_set_irq_funcs()
820 adev->jpeg.inst[i].irq.num_types = 1; in jpeg_v4_0_5_set_irq_funcs()
821 adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs; in jpeg_v4_0_5_set_irq_funcs()