79 	adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;  in jpeg_v4_0_3_early_init()
89  * jpeg_v4_0_3_sw_init - sw init for JPEG block
101 	for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_sw_init()
102 		/* JPEG TRAP */  in jpeg_v4_0_3_sw_init()
104 				amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);  in jpeg_v4_0_3_sw_init()
117 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_sw_init()
118 		jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_sw_init()
120 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_sw_init()
121 			ring = &adev->jpeg.inst[i].ring_dec[j];  in jpeg_v4_0_3_sw_init()
123 			ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);  in jpeg_v4_0_3_sw_init()
138 			sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);  in jpeg_v4_0_3_sw_init()
139 			r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v4_0_3_sw_init()
144 			adev->jpeg.internal.jpeg_pitch[j] =  in jpeg_v4_0_3_sw_init()
146 			adev->jpeg.inst[i].external.jpeg_pitch[j] =  in jpeg_v4_0_3_sw_init()
148 					JPEG, jpeg_inst,  in jpeg_v4_0_3_sw_init()
157 			dev_err(adev->dev, "Failed to initialize jpeg ras block!\n");  in jpeg_v4_0_3_sw_init()
166  * jpeg_v4_0_3_sw_fini - sw fini for JPEG block
170  * JPEG suspend and free up sw allocation
210 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {  in jpeg_v4_0_3_start_sriov()
211 		jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_start_sriov()
222 		for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) {  in jpeg_v4_0_3_start_sriov()
223 			ring = &adev->jpeg.inst[i].ring_dec[j];  in jpeg_v4_0_3_start_sriov()
226 			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);  in jpeg_v4_0_3_start_sriov()
228 			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);  in jpeg_v4_0_3_start_sriov()
230 			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE);  in jpeg_v4_0_3_start_sriov()
292 			DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n",  in jpeg_v4_0_3_start_sriov()
300  * jpeg_v4_0_3_hw_init - start and test JPEG block
317 			for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_hw_init()
318 				ring = &adev->jpeg.inst[i].ring_dec[j];  in jpeg_v4_0_3_hw_init()
326 		for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_hw_init()
327 			jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_hw_init()
329 			ring = adev->jpeg.inst[i].ring_dec;  in jpeg_v4_0_3_hw_init()
336 					adev->jpeg.inst[i].aid_id);  in jpeg_v4_0_3_hw_init()
338 			for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_hw_init()
339 				ring = &adev->jpeg.inst[i].ring_dec[j];  in jpeg_v4_0_3_hw_init()
363  * Stop the JPEG block, mark ring as not ready any more
370 	cancel_delayed_work_sync(&adev->jpeg.idle_work);  in jpeg_v4_0_3_hw_fini()
373 		if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)  in jpeg_v4_0_3_hw_fini()
381  * jpeg_v4_0_3_suspend - suspend JPEG block
385  * HW fini and suspend JPEG block
402  * jpeg_v4_0_3_resume - resume JPEG block
406  * Resume firmware and hw init JPEG block
427 	jpeg_inst = GET_INST(JPEG, inst_idx);  in jpeg_v4_0_3_disable_clock_gating()
428 	data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);  in jpeg_v4_0_3_disable_clock_gating()
438 	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_3_disable_clock_gating()
440 	data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);  in jpeg_v4_0_3_disable_clock_gating()
442 	for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)  in jpeg_v4_0_3_disable_clock_gating()
444 	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);  in jpeg_v4_0_3_disable_clock_gating()
452 	jpeg_inst = GET_INST(JPEG, inst_idx);  in jpeg_v4_0_3_enable_clock_gating()
453 	data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);  in jpeg_v4_0_3_enable_clock_gating()
463 	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_3_enable_clock_gating()
465 	data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);  in jpeg_v4_0_3_enable_clock_gating()
467 	for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)  in jpeg_v4_0_3_enable_clock_gating()
469 	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);  in jpeg_v4_0_3_enable_clock_gating()
473  * jpeg_v4_0_3_start - start JPEG block
477  * Setup and start the JPEG block
484 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_start()
485 		jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_start()
487 		WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,  in jpeg_v4_0_3_start()
490 			JPEG, jpeg_inst, regUVD_PGFSM_STATUS,  in jpeg_v4_0_3_start()
496 		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
500 		/* JPEG disable CGC */  in jpeg_v4_0_3_start()
504 		WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG,  in jpeg_v4_0_3_start()
506 		WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG,  in jpeg_v4_0_3_start()
510 		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,  in jpeg_v4_0_3_start()
513 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_start()
516 			ring = &adev->jpeg.inst[i].ring_dec[j];  in jpeg_v4_0_3_start()
519 			WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
524 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
527 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
532 				JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
536 				JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
539 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
542 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
545 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
548 			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_start()
552 				JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR,  in jpeg_v4_0_3_start()
561  * jpeg_v4_0_3_stop - stop JPEG block
565  * stop the JPEG block
571 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_stop()
572 		jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_stop()
574 		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),  in jpeg_v4_0_3_stop()
581 		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,  in jpeg_v4_0_3_stop()
586 		WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,  in jpeg_v4_0_3_stop()
589 			JPEG, jpeg_inst, regUVD_PGFSM_STATUS,  in jpeg_v4_0_3_stop()
610 		JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,  in jpeg_v4_0_3_dec_ring_get_rptr()
629 			JPEG, GET_INST(JPEG, ring->me),  in jpeg_v4_0_3_dec_ring_get_wptr()
636 	/* JPEG engine access for HDP flush doesn't work when RRMT is enabled.  in jpeg_v4_0_3_ring_emit_hdp_flush()
637 	 * This is a workaround to avoid any HDP flush through JPEG ring.  in jpeg_v4_0_3_ring_emit_hdp_flush()
656 		WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),  in jpeg_v4_0_3_dec_ring_set_wptr()
916 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_is_idle()
917 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_is_idle()
921 					 JPEG, GET_INST(JPEG, i),  in jpeg_v4_0_3_is_idle()
938 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_wait_for_idle()
939 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_wait_for_idle()
943 				JPEG, GET_INST(JPEG, i),  in jpeg_v4_0_3_wait_for_idle()
959 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_set_clockgating_state()
978 		adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;  in jpeg_v4_0_3_set_powergating_state()
982 	if (state == adev->jpeg.cur_state)  in jpeg_v4_0_3_set_powergating_state()
991 		adev->jpeg.cur_state = state;  in jpeg_v4_0_3_set_powergating_state()
1011 	DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");  in jpeg_v4_0_3_process_interrupt()
1013 	for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)  in jpeg_v4_0_3_process_interrupt()
1014 		if (adev->jpeg.inst[inst].aid_id == i)  in jpeg_v4_0_3_process_interrupt()
1017 	if (inst >= adev->jpeg.num_jpeg_inst) {  in jpeg_v4_0_3_process_interrupt()
1019 			      "Interrupt received for unknown JPEG instance %d",  in jpeg_v4_0_3_process_interrupt()
1026 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);  in jpeg_v4_0_3_process_interrupt()
1029 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);  in jpeg_v4_0_3_process_interrupt()
1032 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);  in jpeg_v4_0_3_process_interrupt()
1035 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);  in jpeg_v4_0_3_process_interrupt()
1038 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);  in jpeg_v4_0_3_process_interrupt()
1041 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);  in jpeg_v4_0_3_process_interrupt()
1044 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);  in jpeg_v4_0_3_process_interrupt()
1047 		amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);  in jpeg_v4_0_3_process_interrupt()
1115 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_set_dec_ring_funcs()
1116 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {  in jpeg_v4_0_3_set_dec_ring_funcs()
1117 			adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;  in jpeg_v4_0_3_set_dec_ring_funcs()
1118 			adev->jpeg.inst[i].ring_dec[j].me = i;  in jpeg_v4_0_3_set_dec_ring_funcs()
1119 			adev->jpeg.inst[i].ring_dec[j].pipe = j;  in jpeg_v4_0_3_set_dec_ring_funcs()
1121 		jpeg_inst = GET_INST(JPEG, i);  in jpeg_v4_0_3_set_dec_ring_funcs()
1122 		adev->jpeg.inst[i].aid_id =  in jpeg_v4_0_3_set_dec_ring_funcs()
1123 			jpeg_inst / adev->jpeg.num_inst_per_aid;  in jpeg_v4_0_3_set_dec_ring_funcs()
1136 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {  in jpeg_v4_0_3_set_irq_funcs()
1137 		adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;  in jpeg_v4_0_3_set_irq_funcs()
1139 	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;  in jpeg_v4_0_3_set_irq_funcs()
1151 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S),
1153 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D),
1155 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S),
1157 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D),
1159 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S),
1161 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D),
1163 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S),
1165 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D),
1167 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S),
1169 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D),
1171 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S),
1173 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D),
1175 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S),
1177 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D),
1179 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S),
1181 	{AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D),
1191 	/* jpeg v4_0_3 only support uncorrectable errors */  in jpeg_v4_0_3_inst_query_ras_error_count()
1206 		dev_warn(adev->dev, "JPEG RAS is not supported\n");  in jpeg_v4_0_3_query_ras_error_count()
1210 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)  in jpeg_v4_0_3_query_ras_error_count()
1228 		dev_warn(adev->dev, "JPEG RAS is not supported\n");  in jpeg_v4_0_3_reset_ras_error_count()
1232 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)  in jpeg_v4_0_3_reset_ras_error_count()
1249 	adev->jpeg.ras = &jpeg_v4_0_3_ras;  in jpeg_v4_0_3_set_ras_funcs()