Lines Matching +full:0 +full:x80004000
37 (offset & 0x1FFFF)
40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
65 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)); in jpeg_v4_0_3_normalizn_reqd()
85 return 0; in jpeg_v4_0_3_early_init()
101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
139 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
150 (j ? (0x40 * j - 0xc80) : 0)); in jpeg_v4_0_3_sw_init()
162 return 0; in jpeg_v4_0_3_sw_init()
201 direct_wt = { {0} }; in jpeg_v4_0_3_start_sriov()
202 struct mmsch_v4_0_cmd_end end = { {0} }; in jpeg_v4_0_3_start_sriov()
210 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v4_0_3_start_sriov()
213 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); in jpeg_v4_0_3_start_sriov()
222 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { in jpeg_v4_0_3_start_sriov()
224 table_size = 0; in jpeg_v4_0_3_start_sriov()
226 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); in jpeg_v4_0_3_start_sriov()
228 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); in jpeg_v4_0_3_start_sriov()
230 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); in jpeg_v4_0_3_start_sriov()
235 header.mjpegdec0[j].init_status = 0; in jpeg_v4_0_3_start_sriov()
239 header.mjpegdec1[j - 4].init_status = 0; in jpeg_v4_0_3_start_sriov()
259 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); in jpeg_v4_0_3_start_sriov()
265 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_3_start_sriov()
267 param = 0x00000001; in jpeg_v4_0_3_start_sriov()
269 tmp = 0; in jpeg_v4_0_3_start_sriov()
271 resp = 0; in jpeg_v4_0_3_start_sriov()
278 if (resp != 0) in jpeg_v4_0_3_start_sriov()
285 "(expected=0x%08x, readback=0x%08x)\n", in jpeg_v4_0_3_start_sriov()
292 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", in jpeg_v4_0_3_start_sriov()
296 return 0; in jpeg_v4_0_3_start_sriov()
316 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v4_0_3_hw_init()
317 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
319 ring->wptr = 0; in jpeg_v4_0_3_hw_init()
320 ring->wptr_old = 0; in jpeg_v4_0_3_hw_init()
326 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_hw_init()
338 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
344 (ring->pipe ? (ring->pipe - 0x15) : 0), in jpeg_v4_0_3_hw_init()
355 return 0; in jpeg_v4_0_3_hw_init()
368 int ret = 0; in jpeg_v4_0_3_hw_fini()
442 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_disable_clock_gating()
467 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_enable_clock_gating()
484 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_start()
498 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); in jpeg_v4_0_3_start()
510 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, in jpeg_v4_0_3_start()
513 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_start()
514 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_start()
526 reg_offset, 0); in jpeg_v4_0_3_start()
530 (0x00000001L | 0x00000002L)); in jpeg_v4_0_3_start()
541 reg_offset, 0); in jpeg_v4_0_3_start()
544 reg_offset, 0); in jpeg_v4_0_3_start()
547 reg_offset, 0x00000002L); in jpeg_v4_0_3_start()
557 return 0; in jpeg_v4_0_3_start()
571 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_stop()
595 return 0; in jpeg_v4_0_3_stop()
611 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_rptr()
631 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_wptr()
658 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : in jpeg_v4_0_3_dec_ring_set_wptr()
659 0), in jpeg_v4_0_3_dec_ring_set_wptr()
675 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_start()
676 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v4_0_3_dec_ring_insert_start()
680 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_start()
681 amdgpu_ring_write(ring, 0x80004000); in jpeg_v4_0_3_dec_ring_insert_start()
695 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_end()
696 amdgpu_ring_write(ring, 0x62a04); in jpeg_v4_0_3_dec_ring_insert_end()
700 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_end()
701 amdgpu_ring_write(ring, 0x00004000); in jpeg_v4_0_3_dec_ring_insert_end()
720 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
724 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
728 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
732 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
736 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
737 amdgpu_ring_write(ring, 0x8); in jpeg_v4_0_3_dec_ring_emit_fence()
740 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); in jpeg_v4_0_3_dec_ring_emit_fence()
741 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
743 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
744 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
747 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
748 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v4_0_3_dec_ring_emit_fence()
751 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
752 amdgpu_ring_write(ring, 0x1); in jpeg_v4_0_3_dec_ring_emit_fence()
754 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
755 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
757 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v4_0_3_dec_ring_emit_fence()
758 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
779 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
782 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_ib()
787 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
791 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
795 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
799 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
803 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
807 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
810 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v4_0_3_dec_ring_emit_ib()
811 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_ib()
814 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
815 amdgpu_ring_write(ring, 0x01400200); in jpeg_v4_0_3_dec_ring_emit_ib()
818 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
819 amdgpu_ring_write(ring, 0x2); in jpeg_v4_0_3_dec_ring_emit_ib()
822 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_ib()
823 amdgpu_ring_write(ring, 0x2); in jpeg_v4_0_3_dec_ring_emit_ib()
838 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
839 amdgpu_ring_write(ring, 0x01400200); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
842 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
846 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
847 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v4_0_3_dec_ring_emit_reg_wait()
848 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
850 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
854 0, 0, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
870 mask = 0xffffffff; in jpeg_v4_0_3_dec_ring_emit_vm_flush()
885 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
886 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v4_0_3_dec_ring_emit_wreg()
887 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_wreg()
889 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
893 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
904 for (i = 0; i < count / 2; i++) { in jpeg_v4_0_3_dec_ring_nop()
905 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_nop()
906 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_nop()
916 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_is_idle()
917 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_is_idle()
918 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_is_idle()
935 int ret = 0; in jpeg_v4_0_3_wait_for_idle()
938 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_wait_for_idle()
939 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_wait_for_idle()
940 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_wait_for_idle()
959 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_clockgating_state()
968 return 0; in jpeg_v4_0_3_set_clockgating_state()
979 return 0; in jpeg_v4_0_3_set_powergating_state()
983 return 0; in jpeg_v4_0_3_set_powergating_state()
1001 return 0; in jpeg_v4_0_3_set_interrupt_state()
1013 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) in jpeg_v4_0_3_process_interrupt()
1021 return 0; in jpeg_v4_0_3_process_interrupt()
1026 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); in jpeg_v4_0_3_process_interrupt()
1051 entry->src_id, entry->src_data[0]); in jpeg_v4_0_3_process_interrupt()
1055 return 0; in jpeg_v4_0_3_process_interrupt()
1082 .align_mask = 0xf,
1115 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_dec_ring_funcs()
1116 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_set_dec_ring_funcs()
1136 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_irq_funcs()
1145 .minor = 0,
1151 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S),
1153 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D),
1155 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S),
1157 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D),
1159 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S),
1161 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D),
1163 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S),
1165 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D),
1167 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S),
1169 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D),
1171 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S),
1173 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D),
1175 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S),
1177 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D),
1179 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S),
1181 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D),
1195 NULL, 0, GET_INST(VCN, jpeg_inst), in jpeg_v4_0_3_inst_query_ras_error_count()
1210 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_query_ras_error_count()
1232 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_reset_ras_error_count()