Lines Matching +full:static +full:- +full:enable
37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings
46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev) in ih_v7_0_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v7_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v7_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v7_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v7_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v7_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v7_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v7_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v7_0_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v7_0_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI); in ih_v7_0_init_register_offset()
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; in ih_v7_0_init_register_offset()
65 if (adev->irq.ih1.ring_size) { in ih_v7_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v7_0_init_register_offset()
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); in ih_v7_0_init_register_offset()
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1); in ih_v7_0_init_register_offset()
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v7_0_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v7_0_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v7_0_init_register_offset()
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1); in ih_v7_0_init_register_offset()
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; in ih_v7_0_init_register_offset()
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
83 * @enabled: Enable/disable timeout flush mechanism
92 static void
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) in force_update_wptr_for_self_int()
119 * ih_v7_0_toggle_ring_interrupts - toggle the interrupt ring buffer
123 * @enable: true - enable the interrupts, false - disable the interrupts
127 static int ih_v7_0_toggle_ring_interrupts(struct amdgpu_device *adev, in ih_v7_0_toggle_ring_interrupts()
129 bool enable) in ih_v7_0_toggle_ring_interrupts() argument
134 ih_regs = &ih->ih_regs; in ih_v7_0_toggle_ring_interrupts()
136 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v7_0_toggle_ring_interrupts()
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in ih_v7_0_toggle_ring_interrupts()
139 if (ih == &adev->irq.ih) in ih_v7_0_toggle_ring_interrupts()
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v7_0_toggle_ring_interrupts()
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) in ih_v7_0_toggle_ring_interrupts()
144 return -ETIMEDOUT; in ih_v7_0_toggle_ring_interrupts()
146 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_toggle_ring_interrupts()
149 if (enable) { in ih_v7_0_toggle_ring_interrupts()
150 ih->enabled = true; in ih_v7_0_toggle_ring_interrupts()
153 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v7_0_toggle_ring_interrupts()
154 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v7_0_toggle_ring_interrupts()
155 ih->enabled = false; in ih_v7_0_toggle_ring_interrupts()
156 ih->rptr = 0; in ih_v7_0_toggle_ring_interrupts()
163 * ih_v7_0_toggle_interrupts - Toggle all the available interrupt ring buffers
166 * @enable: enable or disable interrupt ring buffers
170 static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable) in ih_v7_0_toggle_interrupts() argument
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_toggle_interrupts()
177 if (ih[i]->ring_size) { in ih_v7_0_toggle_interrupts()
178 r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable); in ih_v7_0_toggle_interrupts()
187 static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in ih_v7_0_rb_cntl()
189 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v7_0_rb_cntl()
192 MC_SPACE, ih->use_bus_addr ? 2 : 4); in ih_v7_0_rb_cntl()
210 static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih) in ih_v7_0_doorbell_rptr()
214 if (ih->use_doorbell) { in ih_v7_0_doorbell_rptr()
217 ih->doorbell_index); in ih_v7_0_doorbell_rptr()
220 ENABLE, 1); in ih_v7_0_doorbell_rptr()
224 ENABLE, 0); in ih_v7_0_doorbell_rptr()
230 * ih_v7_0_enable_ring - enable an ih ring buffer
235 * Enable an ih ring buffer (IH_V7_0)
237 static int ih_v7_0_enable_ring(struct amdgpu_device *adev, in ih_v7_0_enable_ring()
243 ih_regs = &ih->ih_regs; in ih_v7_0_enable_ring()
245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ in ih_v7_0_enable_ring()
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in ih_v7_0_enable_ring()
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in ih_v7_0_enable_ring()
249 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v7_0_enable_ring()
251 if (ih == &adev->irq.ih) in ih_v7_0_enable_ring()
252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); in ih_v7_0_enable_ring()
253 if (ih == &adev->irq.ih1) { in ih_v7_0_enable_ring()
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in ih_v7_0_enable_ring()
261 return -ETIMEDOUT; in ih_v7_0_enable_ring()
264 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_enable_ring()
267 if (ih == &adev->irq.ih) { in ih_v7_0_enable_ring()
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v7_0_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v7_0_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v7_0_enable_ring()
275 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v7_0_enable_ring()
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih)); in ih_v7_0_enable_ring()
283 * ih_v7_0_irq_init - init and enable the interrupt ring
288 * enable the RLC, disable interrupts, enable the IH
289 * ring buffer and enable it.
293 static int ih_v7_0_irq_init(struct amdgpu_device *adev) in ih_v7_0_irq_init()
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v7_0_irq_init()
306 adev->nbio.funcs->ih_control(adev); in ih_v7_0_irq_init()
308 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || in ih_v7_0_irq_init()
309 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { in ih_v7_0_irq_init()
310 if (ih[0]->use_bus_addr) { in ih_v7_0_irq_init()
319 if (ih[i]->ring_size) { in ih_v7_0_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v7_0_irq_init()
328 ih[0]->doorbell_index); in ih_v7_0_irq_init()
350 if (adev->irq.ih1.ring_size) { in ih_v7_0_irq_init()
364 pci_set_master(adev->pdev); in ih_v7_0_irq_init()
366 /* enable interrupts */ in ih_v7_0_irq_init()
370 /* enable wptr force update for self int */ in ih_v7_0_irq_init()
373 if (adev->irq.ih_soft.ring_size) in ih_v7_0_irq_init()
374 adev->irq.ih_soft.enabled = true; in ih_v7_0_irq_init()
380 * ih_v7_0_irq_disable - disable interrupts
386 static void ih_v7_0_irq_disable(struct amdgpu_device *adev) in ih_v7_0_irq_disable()
396 * ih_v7_0_get_wptr() - get the IH ring buffer wptr
406 static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev, in ih_v7_0_get_wptr()
412 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v7_0_get_wptr()
413 ih_regs = &ih->ih_regs; in ih_v7_0_get_wptr()
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v7_0_get_wptr()
427 tmp = (wptr + 32) & ih->ptr_mask; in ih_v7_0_get_wptr()
428 dev_warn(adev->dev, "IH ring buffer overflow " in ih_v7_0_get_wptr()
430 wptr, ih->rptr, tmp); in ih_v7_0_get_wptr()
431 ih->rptr = tmp; in ih_v7_0_get_wptr()
433 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v7_0_get_wptr()
435 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_get_wptr()
441 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_get_wptr()
443 return (wptr & ih->ptr_mask); in ih_v7_0_get_wptr()
447 * ih_v7_0_irq_rearm - rearm IRQ if lost
453 static void ih_v7_0_irq_rearm(struct amdgpu_device *adev, in ih_v7_0_irq_rearm()
460 ih_regs = &ih->ih_regs; in ih_v7_0_irq_rearm()
462 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ in ih_v7_0_irq_rearm()
464 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v7_0_irq_rearm()
465 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v7_0_irq_rearm()
466 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_irq_rearm()
473 * ih_v7_0_set_rptr - set the IH ring buffer rptr
478 static void ih_v7_0_set_rptr(struct amdgpu_device *adev, in ih_v7_0_set_rptr()
483 if (ih->use_doorbell) { in ih_v7_0_set_rptr()
485 *ih->rptr_cpu = ih->rptr; in ih_v7_0_set_rptr()
486 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_set_rptr()
491 ih_regs = &ih->ih_regs; in ih_v7_0_set_rptr()
492 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v7_0_set_rptr()
497 * ih_v7_0_self_irq - dispatch work for ring 1
505 static int ih_v7_0_self_irq(struct amdgpu_device *adev, in ih_v7_0_self_irq()
509 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v7_0_self_irq()
511 switch (entry->ring_id) { in ih_v7_0_self_irq()
513 *adev->irq.ih1.wptr_cpu = wptr; in ih_v7_0_self_irq()
514 schedule_work(&adev->irq.ih1_work); in ih_v7_0_self_irq()
521 static const struct amdgpu_irq_src_funcs ih_v7_0_self_irq_funcs = {
525 static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev) in ih_v7_0_set_self_irq_funcs()
527 adev->irq.self_irq.num_types = 0; in ih_v7_0_set_self_irq_funcs()
528 adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs; in ih_v7_0_set_self_irq_funcs()
531 static int ih_v7_0_early_init(void *handle) in ih_v7_0_early_init()
540 static int ih_v7_0_sw_init(void *handle) in ih_v7_0_sw_init()
547 &adev->irq.self_irq); in ih_v7_0_sw_init()
556 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; in ih_v7_0_sw_init()
557 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); in ih_v7_0_sw_init()
561 adev->irq.ih.use_doorbell = true; in ih_v7_0_sw_init()
562 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; in ih_v7_0_sw_init()
564 if (!(adev->flags & AMD_IS_APU)) { in ih_v7_0_sw_init()
565 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v7_0_sw_init()
570 adev->irq.ih1.use_doorbell = true; in ih_v7_0_sw_init()
571 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v7_0_sw_init()
577 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); in ih_v7_0_sw_init()
586 static int ih_v7_0_sw_fini(void *handle) in ih_v7_0_sw_fini()
595 static int ih_v7_0_hw_init(void *handle) in ih_v7_0_hw_init()
607 static int ih_v7_0_hw_fini(void *handle) in ih_v7_0_hw_fini()
616 static int ih_v7_0_suspend(void *handle) in ih_v7_0_suspend()
623 static int ih_v7_0_resume(void *handle) in ih_v7_0_resume()
630 static bool ih_v7_0_is_idle(void *handle) in ih_v7_0_is_idle()
636 static int ih_v7_0_wait_for_idle(void *handle) in ih_v7_0_wait_for_idle()
639 return -ETIMEDOUT; in ih_v7_0_wait_for_idle()
642 static int ih_v7_0_soft_reset(void *handle) in ih_v7_0_soft_reset()
648 static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev, in ih_v7_0_update_clockgating_state()
649 bool enable) in ih_v7_0_update_clockgating_state() argument
653 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { in ih_v7_0_update_clockgating_state()
655 field_val = enable ? 0 : 1; in ih_v7_0_update_clockgating_state()
673 static int ih_v7_0_set_clockgating_state(void *handle, in ih_v7_0_set_clockgating_state()
683 static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev, in ih_v7_0_update_ih_mem_power_gating()
684 bool enable) in ih_v7_0_update_ih_mem_power_gating() argument
695 if (enable) { in ih_v7_0_update_ih_mem_power_gating()
710 /* re-enable power cntl */ in ih_v7_0_update_ih_mem_power_gating()
728 /* re-enable power cntl*/ in ih_v7_0_update_ih_mem_power_gating()
736 static int ih_v7_0_set_powergating_state(void *handle, in ih_v7_0_set_powergating_state()
740 bool enable = (state == AMD_PG_STATE_GATE); in ih_v7_0_set_powergating_state() local
742 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG) in ih_v7_0_set_powergating_state()
743 ih_v7_0_update_ih_mem_power_gating(adev, enable); in ih_v7_0_set_powergating_state()
748 static void ih_v7_0_get_clockgating_state(void *handle, u64 *flags) in ih_v7_0_get_clockgating_state()
758 static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
778 static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
785 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev) in ih_v7_0_set_interrupt_funcs()
787 adev->irq.ih_funcs = &ih_v7_0_funcs; in ih_v7_0_set_interrupt_funcs()