48 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_init_register_offset()  local
53 		ih_regs = &adev->irq.ih.ih_regs;  in ih_v6_0_init_register_offset()
54 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);  in ih_v6_0_init_register_offset()
55 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);  in ih_v6_0_init_register_offset()
56 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);  in ih_v6_0_init_register_offset()
57 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);  in ih_v6_0_init_register_offset()
58 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);  in ih_v6_0_init_register_offset()
59 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);  in ih_v6_0_init_register_offset()
60 		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);  in ih_v6_0_init_register_offset()
61 		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);  in ih_v6_0_init_register_offset()
62 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;  in ih_v6_0_init_register_offset()
66 		ih_regs = &adev->irq.ih1.ih_regs;  in ih_v6_0_init_register_offset()
67 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);  in ih_v6_0_init_register_offset()
68 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);  in ih_v6_0_init_register_offset()
69 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);  in ih_v6_0_init_register_offset()
70 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);  in ih_v6_0_init_register_offset()
71 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);  in ih_v6_0_init_register_offset()
72 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);  in ih_v6_0_init_register_offset()
73 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;  in ih_v6_0_init_register_offset()
131 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_toggle_ring_interrupts()  local
134 	ih_regs = &ih->ih_regs;  in ih_v6_0_toggle_ring_interrupts()
136 	tmp = RREG32(ih_regs->ih_rb_cntl);  in ih_v6_0_toggle_ring_interrupts()
145 			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))  in ih_v6_0_toggle_ring_interrupts()
148 			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_toggle_ring_interrupts()
154 			if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))  in ih_v6_0_toggle_ring_interrupts()
157 			WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_toggle_ring_interrupts()
171 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))  in ih_v6_0_toggle_ring_interrupts()
174 		WREG32(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_toggle_ring_interrupts()
181 		WREG32(ih_regs->ih_rb_rptr, 0);  in ih_v6_0_toggle_ring_interrupts()
182 		WREG32(ih_regs->ih_rb_wptr, 0);  in ih_v6_0_toggle_ring_interrupts()
268 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_enable_ring()  local
271 	ih_regs = &ih->ih_regs;  in ih_v6_0_enable_ring()
274 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in ih_v6_0_enable_ring()
275 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in ih_v6_0_enable_ring()
277 	tmp = RREG32(ih_regs->ih_rb_cntl);  in ih_v6_0_enable_ring()
287 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in ih_v6_0_enable_ring()
292 		WREG32(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_enable_ring()
297 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in ih_v6_0_enable_ring()
298 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in ih_v6_0_enable_ring()
302 	WREG32(ih_regs->ih_rb_wptr, 0);  in ih_v6_0_enable_ring()
303 	WREG32(ih_regs->ih_rb_rptr, 0);  in ih_v6_0_enable_ring()
305 	WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih));  in ih_v6_0_enable_ring()
438 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_get_wptr()  local
441 	ih_regs = &ih->ih_regs;  in ih_v6_0_get_wptr()
446 	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);  in ih_v6_0_get_wptr()
461 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in ih_v6_0_get_wptr()
463 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_get_wptr()
469 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_0_get_wptr()
486 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_irq_rearm()  local
488 	ih_regs = &ih->ih_regs;  in ih_v6_0_irq_rearm()
492 		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);  in ih_v6_0_irq_rearm()
511 	struct amdgpu_ih_regs *ih_regs;  in ih_v6_0_set_rptr()  local
521 		ih_regs = &ih->ih_regs;  in ih_v6_0_set_rptr()
522 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in ih_v6_0_set_rptr()