Lines Matching +full:static +full:- +full:enable
37 static void ih_v6_0_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
46 static void ih_v6_0_init_register_offset(struct amdgpu_device *adev) in ih_v6_0_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_0_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_0_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI); in ih_v6_0_init_register_offset()
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; in ih_v6_0_init_register_offset()
65 if (adev->irq.ih1.ring_size) { in ih_v6_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_0_init_register_offset()
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); in ih_v6_0_init_register_offset()
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1); in ih_v6_0_init_register_offset()
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v6_0_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v6_0_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v6_0_init_register_offset()
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1); in ih_v6_0_init_register_offset()
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; in ih_v6_0_init_register_offset()
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
83 * @enabled: Enable/disable timeout flush mechanism
92 static void
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) in force_update_wptr_for_self_int()
119 * ih_v6_0_toggle_ring_interrupts - toggle the interrupt ring buffer
123 * @enable: true - enable the interrupts, false - disable the interrupts
127 static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev, in ih_v6_0_toggle_ring_interrupts()
129 bool enable) in ih_v6_0_toggle_ring_interrupts() argument
134 ih_regs = &ih->ih_regs; in ih_v6_0_toggle_ring_interrupts()
136 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v6_0_toggle_ring_interrupts()
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in ih_v6_0_toggle_ring_interrupts()
139 if (enable) { in ih_v6_0_toggle_ring_interrupts()
145 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) in ih_v6_0_toggle_ring_interrupts()
146 return -ETIMEDOUT; in ih_v6_0_toggle_ring_interrupts()
148 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
154 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) in ih_v6_0_toggle_ring_interrupts()
155 return -ETIMEDOUT; in ih_v6_0_toggle_ring_interrupts()
157 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
167 if (ih == &adev->irq.ih) in ih_v6_0_toggle_ring_interrupts()
168 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_0_toggle_ring_interrupts()
171 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) in ih_v6_0_toggle_ring_interrupts()
172 return -ETIMEDOUT; in ih_v6_0_toggle_ring_interrupts()
174 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
177 if (enable) { in ih_v6_0_toggle_ring_interrupts()
178 ih->enabled = true; in ih_v6_0_toggle_ring_interrupts()
181 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_toggle_ring_interrupts()
182 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_toggle_ring_interrupts()
183 ih->enabled = false; in ih_v6_0_toggle_ring_interrupts()
184 ih->rptr = 0; in ih_v6_0_toggle_ring_interrupts()
191 * ih_v6_0_toggle_interrupts - Toggle all the available interrupt ring buffers
194 * @enable: enable or disable interrupt ring buffers
198 static int ih_v6_0_toggle_interrupts(struct amdgpu_device *adev, bool enable) in ih_v6_0_toggle_interrupts() argument
200 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_toggle_interrupts()
205 if (ih[i]->ring_size) { in ih_v6_0_toggle_interrupts()
206 r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable); in ih_v6_0_toggle_interrupts()
215 static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in ih_v6_0_rb_cntl()
217 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_0_rb_cntl()
220 MC_SPACE, ih->use_bus_addr ? 2 : 4); in ih_v6_0_rb_cntl()
238 static uint32_t ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih) in ih_v6_0_doorbell_rptr()
242 if (ih->use_doorbell) { in ih_v6_0_doorbell_rptr()
245 ih->doorbell_index); in ih_v6_0_doorbell_rptr()
248 ENABLE, 1); in ih_v6_0_doorbell_rptr()
252 ENABLE, 0); in ih_v6_0_doorbell_rptr()
258 * ih_v6_0_enable_ring - enable an ih ring buffer
263 * Enable an ih ring buffer (IH_V6_0)
265 static int ih_v6_0_enable_ring(struct amdgpu_device *adev, in ih_v6_0_enable_ring()
271 ih_regs = &ih->ih_regs; in ih_v6_0_enable_ring()
273 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ in ih_v6_0_enable_ring()
274 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in ih_v6_0_enable_ring()
275 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in ih_v6_0_enable_ring()
277 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v6_0_enable_ring()
279 if (ih == &adev->irq.ih) in ih_v6_0_enable_ring()
280 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); in ih_v6_0_enable_ring()
281 if (ih == &adev->irq.ih1) { in ih_v6_0_enable_ring()
287 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in ih_v6_0_enable_ring()
289 return -ETIMEDOUT; in ih_v6_0_enable_ring()
292 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_enable_ring()
295 if (ih == &adev->irq.ih) { in ih_v6_0_enable_ring()
297 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
298 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
302 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_enable_ring()
303 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_enable_ring()
305 WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih)); in ih_v6_0_enable_ring()
311 * ih_v6_0_irq_init - init and enable the interrupt ring
316 * enable the RLC, disable interrupts, enable the IH
317 * ring buffer and enable it.
321 static int ih_v6_0_irq_init(struct amdgpu_device *adev) in ih_v6_0_irq_init()
323 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_irq_init()
334 adev->nbio.funcs->ih_control(adev); in ih_v6_0_irq_init()
336 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || in ih_v6_0_irq_init()
337 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { in ih_v6_0_irq_init()
338 if (ih[0]->use_bus_addr) { in ih_v6_0_irq_init()
347 if (ih[i]->ring_size) { in ih_v6_0_irq_init()
355 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_0_irq_init()
356 ih[0]->doorbell_index); in ih_v6_0_irq_init()
378 if (adev->irq.ih1.ring_size) { in ih_v6_0_irq_init()
392 pci_set_master(adev->pdev); in ih_v6_0_irq_init()
394 /* enable interrupts */ in ih_v6_0_irq_init()
398 /* enable wptr force update for self int */ in ih_v6_0_irq_init()
401 if (adev->irq.ih_soft.ring_size) in ih_v6_0_irq_init()
402 adev->irq.ih_soft.enabled = true; in ih_v6_0_irq_init()
408 * ih_v6_0_irq_disable - disable interrupts
414 static void ih_v6_0_irq_disable(struct amdgpu_device *adev) in ih_v6_0_irq_disable()
424 * ih_v6_0_get_wptr - get the IH ring buffer wptr
434 static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev, in ih_v6_0_get_wptr()
440 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_0_get_wptr()
441 ih_regs = &ih->ih_regs; in ih_v6_0_get_wptr()
446 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
455 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_0_get_wptr()
456 dev_warn(adev->dev, "IH ring buffer overflow " in ih_v6_0_get_wptr()
458 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
459 ih->rptr = tmp; in ih_v6_0_get_wptr()
461 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_0_get_wptr()
463 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_get_wptr()
469 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_get_wptr()
471 return (wptr & ih->ptr_mask); in ih_v6_0_get_wptr()
475 * ih_v6_0_irq_rearm - rearm IRQ if lost
481 static void ih_v6_0_irq_rearm(struct amdgpu_device *adev, in ih_v6_0_irq_rearm()
488 ih_regs = &ih->ih_regs; in ih_v6_0_irq_rearm()
490 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ in ih_v6_0_irq_rearm()
492 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
493 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_0_irq_rearm()
494 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_irq_rearm()
501 * ih_v6_0_set_rptr - set the IH ring buffer rptr
508 static void ih_v6_0_set_rptr(struct amdgpu_device *adev, in ih_v6_0_set_rptr()
513 if (ih->use_doorbell) { in ih_v6_0_set_rptr()
515 *ih->rptr_cpu = ih->rptr; in ih_v6_0_set_rptr()
516 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_set_rptr()
521 ih_regs = &ih->ih_regs; in ih_v6_0_set_rptr()
522 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_0_set_rptr()
527 * ih_v6_0_self_irq - dispatch work for ring 1
535 static int ih_v6_0_self_irq(struct amdgpu_device *adev, in ih_v6_0_self_irq()
539 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_0_self_irq()
541 switch (entry->ring_id) { in ih_v6_0_self_irq()
543 *adev->irq.ih1.wptr_cpu = wptr; in ih_v6_0_self_irq()
544 schedule_work(&adev->irq.ih1_work); in ih_v6_0_self_irq()
552 static const struct amdgpu_irq_src_funcs ih_v6_0_self_irq_funcs = {
556 static void ih_v6_0_set_self_irq_funcs(struct amdgpu_device *adev) in ih_v6_0_set_self_irq_funcs()
558 adev->irq.self_irq.num_types = 0; in ih_v6_0_set_self_irq_funcs()
559 adev->irq.self_irq.funcs = &ih_v6_0_self_irq_funcs; in ih_v6_0_set_self_irq_funcs()
562 static int ih_v6_0_early_init(void *handle) in ih_v6_0_early_init()
571 static int ih_v6_0_sw_init(void *handle) in ih_v6_0_sw_init()
578 &adev->irq.self_irq); in ih_v6_0_sw_init()
587 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; in ih_v6_0_sw_init()
588 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); in ih_v6_0_sw_init()
592 adev->irq.ih.use_doorbell = true; in ih_v6_0_sw_init()
593 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; in ih_v6_0_sw_init()
595 if (!(adev->flags & AMD_IS_APU)) { in ih_v6_0_sw_init()
596 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v6_0_sw_init()
601 adev->irq.ih1.use_doorbell = true; in ih_v6_0_sw_init()
602 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v6_0_sw_init()
608 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); in ih_v6_0_sw_init()
617 static int ih_v6_0_sw_fini(void *handle) in ih_v6_0_sw_fini()
626 static int ih_v6_0_hw_init(void *handle) in ih_v6_0_hw_init()
638 static int ih_v6_0_hw_fini(void *handle) in ih_v6_0_hw_fini()
647 static int ih_v6_0_suspend(void *handle) in ih_v6_0_suspend()
654 static int ih_v6_0_resume(void *handle) in ih_v6_0_resume()
661 static bool ih_v6_0_is_idle(void *handle) in ih_v6_0_is_idle()
667 static int ih_v6_0_wait_for_idle(void *handle) in ih_v6_0_wait_for_idle()
670 return -ETIMEDOUT; in ih_v6_0_wait_for_idle()
673 static int ih_v6_0_soft_reset(void *handle) in ih_v6_0_soft_reset()
679 static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev, in ih_v6_0_update_clockgating_state()
680 bool enable) in ih_v6_0_update_clockgating_state() argument
684 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { in ih_v6_0_update_clockgating_state()
686 field_val = enable ? 0 : 1; in ih_v6_0_update_clockgating_state()
702 static int ih_v6_0_set_clockgating_state(void *handle, in ih_v6_0_set_clockgating_state()
712 static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev, in ih_v6_0_update_ih_mem_power_gating()
713 bool enable) in ih_v6_0_update_ih_mem_power_gating() argument
724 if (enable) { in ih_v6_0_update_ih_mem_power_gating()
739 /* re-enable power cntl */ in ih_v6_0_update_ih_mem_power_gating()
757 /* re-enable power cntl*/ in ih_v6_0_update_ih_mem_power_gating()
765 static int ih_v6_0_set_powergating_state(void *handle, in ih_v6_0_set_powergating_state()
769 bool enable = (state == AMD_PG_STATE_GATE); in ih_v6_0_set_powergating_state() local
771 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG) in ih_v6_0_set_powergating_state()
772 ih_v6_0_update_ih_mem_power_gating(adev, enable); in ih_v6_0_set_powergating_state()
777 static void ih_v6_0_get_clockgating_state(void *handle, u64 *flags) in ih_v6_0_get_clockgating_state()
785 static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
805 static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
812 static void ih_v6_0_set_interrupt_funcs(struct amdgpu_device *adev) in ih_v6_0_set_interrupt_funcs()
814 adev->irq.ih_funcs = &ih_v6_0_funcs; in ih_v6_0_set_interrupt_funcs()