Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
112 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
123 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers()
179 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
195 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
198 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
204 * gmc_v8_0_init_microcode - load ucode images from disk
210 * Returns 0 on success, error on failure.
219 switch (adev->asic_type) { in gmc_v8_0_init_microcode()
224 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || in gmc_v8_0_init_microcode()
225 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) in gmc_v8_0_init_microcode()
231 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) in gmc_v8_0_init_microcode()
237 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { in gmc_v8_0_init_microcode()
242 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) in gmc_v8_0_init_microcode()
252 return 0; in gmc_v8_0_init_microcode()
254 return -EINVAL; in gmc_v8_0_init_microcode()
257 err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name); in gmc_v8_0_init_microcode()
260 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
266 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
271 * Returns 0 on success, error on failure.
281 /* Skip MC ucode loading on SR-IOV capable boards. in gmc_v8_0_tonga_mc_load_microcode()
287 return 0; in gmc_v8_0_tonga_mc_load_microcode()
289 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
290 return -EINVAL; in gmc_v8_0_tonga_mc_load_microcode()
292 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
293 amdgpu_ucode_print_mc_hdr(&hdr->header); in gmc_v8_0_tonga_mc_load_microcode()
295 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
296 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); in gmc_v8_0_tonga_mc_load_microcode()
298 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
299 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in gmc_v8_0_tonga_mc_load_microcode()
301 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
305 if (running == 0) { in gmc_v8_0_tonga_mc_load_microcode()
307 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
308 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
311 for (i = 0; i < regs_size; i++) { in gmc_v8_0_tonga_mc_load_microcode()
316 for (i = 0; i < ucode_size; i++) in gmc_v8_0_tonga_mc_load_microcode()
320 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
321 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
325 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v8_0_tonga_mc_load_microcode()
331 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v8_0_tonga_mc_load_microcode()
339 return 0; in gmc_v8_0_tonga_mc_load_microcode()
350 /* Skip MC ucode loading on SR-IOV capable boards. in gmc_v8_0_polaris_mc_load_microcode()
356 return 0; in gmc_v8_0_polaris_mc_load_microcode()
358 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
359 return -EINVAL; in gmc_v8_0_polaris_mc_load_microcode()
361 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
362 amdgpu_ucode_print_mc_hdr(&hdr->header); in gmc_v8_0_polaris_mc_load_microcode()
364 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
365 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); in gmc_v8_0_polaris_mc_load_microcode()
367 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
368 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in gmc_v8_0_polaris_mc_load_microcode()
370 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
373 data &= ~(0x40); in gmc_v8_0_polaris_mc_load_microcode()
377 for (i = 0; i < regs_size; i++) { in gmc_v8_0_polaris_mc_load_microcode()
382 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
383 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
386 for (i = 0; i < ucode_size; i++) in gmc_v8_0_polaris_mc_load_microcode()
390 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
391 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_polaris_mc_load_microcode()
395 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v8_0_polaris_mc_load_microcode()
397 if (data & 0x80) in gmc_v8_0_polaris_mc_load_microcode()
402 return 0; in gmc_v8_0_polaris_mc_load_microcode()
408 u64 base = 0; in gmc_v8_0_vram_gtt_location()
411 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
420 * gmc_v8_0_mc_program - program the GPU memory controller
433 for (i = 0, j = 0; i < 32; i++, j += 0x6) { in gmc_v8_0_mc_program()
434 WREG32((0xb05 + j), 0x00000000); in gmc_v8_0_mc_program()
435 WREG32((0xb06 + j), 0x00000000); in gmc_v8_0_mc_program()
436 WREG32((0xb07 + j), 0x00000000); in gmc_v8_0_mc_program()
437 WREG32((0xb08 + j), 0x00000000); in gmc_v8_0_mc_program()
438 WREG32((0xb09 + j), 0x00000000); in gmc_v8_0_mc_program()
440 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); in gmc_v8_0_mc_program()
443 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
445 if (adev->mode_info.num_crtc) { in gmc_v8_0_mc_program()
453 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
458 adev->gmc.vram_start >> 12); in gmc_v8_0_mc_program()
460 adev->gmc.vram_end >> 12); in gmc_v8_0_mc_program()
462 adev->mem_scratch.gpu_addr >> 12); in gmc_v8_0_mc_program()
465 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
466 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
469 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
471 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); in gmc_v8_0_mc_program()
474 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v8_0_mc_program()
475 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v8_0_mc_program()
476 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v8_0_mc_program()
478 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
483 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
491 * gmc_v8_0_mc_init - initialize the memory controller driver params
497 * Returns 0 for success.
504 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); in gmc_v8_0_mc_init()
505 if (!adev->gmc.vram_width) { in gmc_v8_0_mc_init()
517 case 0: in gmc_v8_0_mc_init()
546 adev->gmc.vram_width = numchan * chansize; in gmc_v8_0_mc_init()
551 if (tmp & 0xffff0000) { in gmc_v8_0_mc_init()
552 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in gmc_v8_0_mc_init()
553 if (tmp & 0xffff) in gmc_v8_0_mc_init()
554 tmp &= 0xffff; in gmc_v8_0_mc_init()
556 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
557 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v8_0_mc_init()
559 if (!(adev->flags & AMD_IS_APU)) { in gmc_v8_0_mc_init()
564 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
565 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
568 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { in gmc_v8_0_mc_init()
569 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; in gmc_v8_0_mc_init()
570 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
574 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
577 if (amdgpu_gart_size == -1) { in gmc_v8_0_mc_init()
578 switch (adev->asic_type) { in gmc_v8_0_mc_init()
584 adev->gmc.gart_size = 256ULL << 20; in gmc_v8_0_mc_init()
590 adev->gmc.gart_size = 1024ULL << 20; in gmc_v8_0_mc_init()
594 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v8_0_mc_init()
597 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v8_0_mc_init()
598 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
600 return 0; in gmc_v8_0_mc_init()
604 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
618 u32 mask = 0x0; in gmc_v8_0_flush_gpu_tlb_pasid()
635 * VMID 0 is the physical GPU addresses as used by the kernel.
636 * VMIDs 1-15 are used for userspace clients and are handled
641 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
653 /* bits 0-15 are the VM contexts0-15 */ in gmc_v8_0_flush_gpu_tlb()
665 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; in gmc_v8_0_emit_flush_gpu_tlb()
668 /* bits 0-15 are the VM contexts0-15 */ in gmc_v8_0_emit_flush_gpu_tlb()
691 * 0 valid
697 * bits 5:1 must be 0.
698 * 0 valid
704 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); in gmc_v8_0_get_vm_pde()
712 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; in gmc_v8_0_get_vm_pte()
717 * gmc_v8_0_set_fault_enable_default - update VM fault handling
746 * gmc_v8_0_set_prt() - set PRT VM fault
755 if (enable && !adev->gmc.prt_warning) { in gmc_v8_0_set_prt()
756 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v8_0_set_prt()
757 adev->gmc.prt_warning = true; in gmc_v8_0_set_prt()
780 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
792 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
793 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
794 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
795 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
796 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
797 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
798 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
799 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
804 * gmc_v8_0_gart_enable - gart enable
809 * sets up the hw for VMIDs 1-15 which are allocated on
812 * Returns 0 for success, errors for failure.
820 if (adev->gart.bo == NULL) { in gmc_v8_0_gart_enable()
821 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v8_0_gart_enable()
822 return -EINVAL; in gmc_v8_0_gart_enable()
824 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); in gmc_v8_0_gart_enable()
825 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v8_0_gart_enable()
833 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v8_0_gart_enable()
850 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
872 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
873 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
876 (u32)(adev->dummy_page_addr >> 12)); in gmc_v8_0_gart_enable()
877 WREG32(mmVM_CONTEXT0_CNTL2, 0); in gmc_v8_0_gart_enable()
880 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
884 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); in gmc_v8_0_gart_enable()
885 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); in gmc_v8_0_gart_enable()
886 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); in gmc_v8_0_gart_enable()
888 /* empty context1-15 */ in gmc_v8_0_gart_enable()
893 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in gmc_v8_0_gart_enable()
894 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
900 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, in gmc_v8_0_gart_enable()
904 /* enable context1-15 */ in gmc_v8_0_gart_enable()
906 (u32)(adev->dummy_page_addr >> 12)); in gmc_v8_0_gart_enable()
919 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
926 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); in gmc_v8_0_gart_enable()
927 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v8_0_gart_enable()
928 (unsigned int)(adev->gmc.gart_size >> 20), in gmc_v8_0_gart_enable()
930 return 0; in gmc_v8_0_gart_enable()
937 if (adev->gart.bo) { in gmc_v8_0_gart_init()
939 return 0; in gmc_v8_0_gart_init()
945 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v8_0_gart_init()
946 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; in gmc_v8_0_gart_init()
951 * gmc_v8_0_gart_disable - gart disable
962 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v8_0_gart_disable()
963 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
966 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
967 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v8_0_gart_disable()
968 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v8_0_gart_disable()
972 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
974 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
978 * gmc_v8_0_vm_decode_fault - print human readable fault info
984 * @pasid: debug logging only - no functional use
994 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, in gmc_v8_0_vm_decode_fault()
995 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; in gmc_v8_0_vm_decode_fault()
1001 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", in gmc_v8_0_vm_decode_fault()
1037 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v8_0_early_init()
1038 adev->gmc.shared_aperture_end = in gmc_v8_0_early_init()
1039 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1040 adev->gmc.private_aperture_start = in gmc_v8_0_early_init()
1041 adev->gmc.shared_aperture_end + 1; in gmc_v8_0_early_init()
1042 adev->gmc.private_aperture_end = in gmc_v8_0_early_init()
1043 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1044 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; in gmc_v8_0_early_init()
1046 return 0; in gmc_v8_0_early_init()
1054 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
1056 return 0; in gmc_v8_0_late_init()
1077 #define mmMC_SEQ_MISC0_FIJI 0xA71
1084 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); in gmc_v8_0_sw_init()
1086 if (adev->flags & AMD_IS_APU) { in gmc_v8_0_sw_init()
1087 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; in gmc_v8_0_sw_init()
1091 if ((adev->asic_type == CHIP_FIJI) || in gmc_v8_0_sw_init()
1092 (adev->asic_type == CHIP_VEGAM)) in gmc_v8_0_sw_init()
1097 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1100 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1104 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1118 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v8_0_sw_init()
1120 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); in gmc_v8_0_sw_init()
1125 adev->need_swiotlb = drm_need_swiotlb(40); in gmc_v8_0_sw_init()
1150 * VMID 0 is reserved for System in gmc_v8_0_sw_init()
1151 * amdgpu graphics/compute will use VMIDs 1-7 in gmc_v8_0_sw_init()
1152 * amdkfd will use VMIDs 8-15 in gmc_v8_0_sw_init()
1154 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1158 if (adev->flags & AMD_IS_APU) { in gmc_v8_0_sw_init()
1162 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1164 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
1167 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), in gmc_v8_0_sw_init()
1169 if (!adev->gmc.vm_fault_info) in gmc_v8_0_sw_init()
1170 return -ENOMEM; in gmc_v8_0_sw_init()
1171 atomic_set(&adev->gmc.vm_fault_info_updated, 0); in gmc_v8_0_sw_init()
1173 return 0; in gmc_v8_0_sw_init()
1182 kfree(adev->gmc.vm_fault_info); in gmc_v8_0_sw_fini()
1185 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_sw_fini()
1187 return 0; in gmc_v8_0_sw_fini()
1199 if (adev->asic_type == CHIP_TONGA) { in gmc_v8_0_hw_init()
1205 } else if (adev->asic_type == CHIP_POLARIS11 || in gmc_v8_0_hw_init()
1206 adev->asic_type == CHIP_POLARIS10 || in gmc_v8_0_hw_init()
1207 adev->asic_type == CHIP_POLARIS12) { in gmc_v8_0_hw_init()
1222 return 0; in gmc_v8_0_hw_init()
1229 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_hw_fini()
1232 return 0; in gmc_v8_0_hw_fini()
1241 return 0; in gmc_v8_0_suspend()
1255 return 0; in gmc_v8_0_resume()
1276 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v8_0_wait_for_idle()
1285 return 0; in gmc_v8_0_wait_for_idle()
1288 return -ETIMEDOUT; in gmc_v8_0_wait_for_idle()
1294 u32 srbm_soft_reset = 0; in gmc_v8_0_check_soft_reset()
1304 if (!(adev->flags & AMD_IS_APU)) in gmc_v8_0_check_soft_reset()
1310 adev->gmc.srbm_soft_reset = srbm_soft_reset; in gmc_v8_0_check_soft_reset()
1314 adev->gmc.srbm_soft_reset = 0; in gmc_v8_0_check_soft_reset()
1323 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_pre_soft_reset()
1324 return 0; in gmc_v8_0_pre_soft_reset()
1328 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v8_0_pre_soft_reset()
1330 return 0; in gmc_v8_0_pre_soft_reset()
1338 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_soft_reset()
1339 return 0; in gmc_v8_0_soft_reset()
1340 srbm_soft_reset = adev->gmc.srbm_soft_reset; in gmc_v8_0_soft_reset()
1347 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v8_0_soft_reset()
1361 return 0; in gmc_v8_0_soft_reset()
1368 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_post_soft_reset()
1369 return 0; in gmc_v8_0_post_soft_reset()
1372 return 0; in gmc_v8_0_post_soft_reset()
1414 return 0; in gmc_v8_0_vm_fault_interrupt_state()
1424 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", in gmc_v8_0_process_interrupt()
1425 entry->src_id, entry->src_data[0]); in gmc_v8_0_process_interrupt()
1426 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); in gmc_v8_0_process_interrupt()
1427 return 0; in gmc_v8_0_process_interrupt()
1437 return 0; in gmc_v8_0_process_interrupt()
1439 amdgpu_vm_update_fault_cache(adev, entry->pasid, in gmc_v8_0_process_interrupt()
1440 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); in gmc_v8_0_process_interrupt()
1448 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", in gmc_v8_0_process_interrupt()
1449 entry->src_id, entry->src_data[0]); in gmc_v8_0_process_interrupt()
1451 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); in gmc_v8_0_process_interrupt()
1453 dev_err(adev->dev, " for process %s pid %d thread %s pid %d\n", in gmc_v8_0_process_interrupt()
1454 task_info->process_name, task_info->tgid, in gmc_v8_0_process_interrupt()
1455 task_info->task_name, task_info->pid); in gmc_v8_0_process_interrupt()
1459 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in gmc_v8_0_process_interrupt()
1461 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in gmc_v8_0_process_interrupt()
1465 entry->pasid); in gmc_v8_0_process_interrupt()
1471 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { in gmc_v8_0_process_interrupt()
1472 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; in gmc_v8_0_process_interrupt()
1477 info->vmid = vmid; in gmc_v8_0_process_interrupt()
1478 info->mc_id = REG_GET_FIELD(status, in gmc_v8_0_process_interrupt()
1481 info->status = status; in gmc_v8_0_process_interrupt()
1482 info->page_addr = addr; in gmc_v8_0_process_interrupt()
1483 info->prot_valid = protections & 0x7 ? true : false; in gmc_v8_0_process_interrupt()
1484 info->prot_read = protections & 0x8 ? true : false; in gmc_v8_0_process_interrupt()
1485 info->prot_write = protections & 0x10 ? true : false; in gmc_v8_0_process_interrupt()
1486 info->prot_exec = protections & 0x20 ? true : false; in gmc_v8_0_process_interrupt()
1488 atomic_set(&adev->gmc.vm_fault_info_updated, 1); in gmc_v8_0_process_interrupt()
1491 return 0; in gmc_v8_0_process_interrupt()
1499 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { in fiji_update_mc_medium_grain_clock_gating()
1579 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { in fiji_update_mc_light_sleep()
1660 return 0; in gmc_v8_0_set_clockgating_state()
1662 switch (adev->asic_type) { in gmc_v8_0_set_clockgating_state()
1672 return 0; in gmc_v8_0_set_clockgating_state()
1678 return 0; in gmc_v8_0_set_powergating_state()
1687 *flags = 0; in gmc_v8_0_get_clockgating_state()
1740 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; in gmc_v8_0_set_gmc_funcs()
1745 adev->gmc.vm_fault.num_types = 1; in gmc_v8_0_set_irq_funcs()
1746 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; in gmc_v8_0_set_irq_funcs()
1752 .minor = 0,
1753 .rev = 0,
1761 .rev = 0,
1769 .rev = 0,