3733 	WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);  in gfx_v8_0_constants_init()
3950 	WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);  in gfx_v8_0_init_save_restore_list()
3989 	WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);  in gfx_v8_0_enable_save_restore_machine()
3996 	WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);  in gfx_v8_0_init_power_gating()
4004 	WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);  in gfx_v8_0_init_power_gating()
4005 	WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);  in gfx_v8_0_init_power_gating()
4012 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_up()
4018 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_down()
4023 	WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);  in cz_enable_cp_power_gating()
4049 	WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);  in gfx_v8_0_rlc_stop()
4057 	WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);  in gfx_v8_0_rlc_reset()
4060 	WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);  in gfx_v8_0_rlc_reset()
4066 	WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);  in gfx_v8_0_rlc_start()
4378 		WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);  in gfx_v8_0_deactivate_hqd()
4564 	WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);  in gfx_v8_0_mqd_commit()
4667 	WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);  in gfx_v8_0_set_mec_doorbell_range()
5318 	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_static_mg_power_gating()
5324 	WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5330 	WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);  in polaris11_enable_gfx_quick_mg_power_gating()
5336 	WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_cg_power_gating()
5342 	WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_pipeline_power_gating()
5627 				WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);  in gfx_v8_0_update_medium_grain_clock_gating()
5630 				WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);  in gfx_v8_0_update_medium_grain_clock_gating()
6428 	WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,  in gfx_v8_0_set_gfx_eop_interrupt_state()
6488 	WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,  in gfx_v8_0_set_priv_reg_fault_state()
6499 	WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,  in gfx_v8_0_set_priv_inst_fault_state()
6564 	WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);  in gfx_v8_0_set_cp_ecc_int_state()
6565 	WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);  in gfx_v8_0_set_cp_ecc_int_state()
6566 	WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);  in gfx_v8_0_set_cp_ecc_int_state()
6567 	WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);  in gfx_v8_0_set_cp_ecc_int_state()
6568 	WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);  in gfx_v8_0_set_cp_ecc_int_state()
6569 	WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6571 	WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6573 	WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6575 	WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6577 	WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6579 	WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6581 	WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6583 	WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,  in gfx_v8_0_set_cp_ecc_int_state()
6609 	WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,  in gfx_v8_0_set_sq_int_state()