Lines Matching refs:macrotile
991 uint32_t *tile, *macrotile; in gfx_v7_0_tiling_mode_table_init() local
994 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1012 macrotile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1119 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1123 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1127 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1131 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1135 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1139 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1143 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1147 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1151 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1155 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1159 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1163 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1167 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1171 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1180 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1302 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1306 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1310 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1314 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1318 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1322 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1326 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1330 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1334 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1338 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1342 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1346 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1350 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1354 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1363 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1472 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1476 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1480 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1484 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1488 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1492 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1496 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1500 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v7_0_tiling_mode_table_init()
1504 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v7_0_tiling_mode_table_init()
1508 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1512 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1516 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1520 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1524 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1533 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()