Lines Matching refs:BANK_WIDTH
84 #define BANK_WIDTH(x) ((x) << 14) macro
408 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
424 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
459 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
514 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
549 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
557 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
581 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
589 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
621 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
649 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
657 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
681 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
689 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
697 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
721 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
729 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
737 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
761 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
769 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
786 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
804 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
812 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
828 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
838 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
846 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
889 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
909 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
917 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
951 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
962 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
979 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
987 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
995 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1003 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1011 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1019 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1035 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1043 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1051 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1085 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1113 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1141 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1175 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1194 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1203 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1211 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1235 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1243 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1251 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
1275 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()