294 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)  in gfx11_kiq_set_resources()  argument
296 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx11_kiq_set_resources()
297 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |  in gfx11_kiq_set_resources()
300 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */  in gfx11_kiq_set_resources()
301 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */  in gfx11_kiq_set_resources()
302 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */  in gfx11_kiq_set_resources()
303 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */  in gfx11_kiq_set_resources()
304 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx11_kiq_set_resources()
305 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx11_kiq_set_resources()
308 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_map_queues()  argument
332 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx11_kiq_map_queues()
334 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_map_queues()
344 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));  in gfx11_kiq_map_queues()
345 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));  in gfx11_kiq_map_queues()
346 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));  in gfx11_kiq_map_queues()
347 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));  in gfx11_kiq_map_queues()
348 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));  in gfx11_kiq_map_queues()
351 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_unmap_queues()  argument
356 	struct amdgpu_device *adev = kiq_ring->adev;  in gfx11_kiq_unmap_queues()
364 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx11_kiq_unmap_queues()
365 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_unmap_queues()
370 	amdgpu_ring_write(kiq_ring,  in gfx11_kiq_unmap_queues()
374 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));  in gfx11_kiq_unmap_queues()
375 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));  in gfx11_kiq_unmap_queues()
376 		amdgpu_ring_write(kiq_ring, seq);  in gfx11_kiq_unmap_queues()
378 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
379 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
380 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
384 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_query_status()  argument
391 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));  in gfx11_kiq_query_status()
392 	amdgpu_ring_write(kiq_ring,  in gfx11_kiq_query_status()
396 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_query_status()
399 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));  in gfx11_kiq_query_status()
400 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));  in gfx11_kiq_query_status()
401 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));  in gfx11_kiq_query_status()
402 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));  in gfx11_kiq_query_status()
405 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_invalidate_tlbs()  argument
409 	gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);  in gfx11_kiq_invalidate_tlbs()
5923 	struct amdgpu_ring *kiq_ring = &kiq->ring;  in gfx_v11_0_ring_preempt_ib()  local
5934 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {  in gfx_v11_0_ring_preempt_ib()
5943 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,  in gfx_v11_0_ring_preempt_ib()
5946 	amdgpu_ring_commit(kiq_ring);  in gfx_v11_0_ring_preempt_ib()