Lines Matching +full:0 +full:xf0ffffff
56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
59 #define regCGTT_WD_CLK_CTRL 0x5086
61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
63 #define regPC_CONFIG_CNTL_1 0x194d
102 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
116 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
118 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
119 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
120 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
121 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
123 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
124 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
126 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
127 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
135 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
137 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
138 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
139 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
140 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
141 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
142 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
143 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
144 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
145 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
146 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
147 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
148 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
149 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
150 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
165 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
166 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
167 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
168 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
169 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
170 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
234 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
246 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
251 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
252 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
253 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
257 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
258 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
259 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
298 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ in gfx11_kiq_set_resources()
299 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx11_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx11_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx11_kiq_set_resources()
304 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
305 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
313 uint32_t me = 0, eng_sel = 0; in gfx11_kiq_map_queues()
318 eng_sel = 0; in gfx11_kiq_map_queues()
321 me = 0; in gfx11_kiq_map_queues()
333 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ in gfx11_kiq_map_queues()
334 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
335 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ in gfx11_kiq_map_queues()
336 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ in gfx11_kiq_map_queues()
340 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ in gfx11_kiq_map_queues()
341 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ in gfx11_kiq_map_queues()
357 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_unmap_queues()
359 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_unmap_queues()
367 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | in gfx11_kiq_unmap_queues()
378 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
379 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
380 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
389 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_query_status()
393 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | in gfx11_kiq_query_status()
394 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | in gfx11_kiq_query_status()
396 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_query_status()
427 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
435 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_init_golden_registers()
436 case IP_VERSION(11, 0, 1): in gfx_v11_0_init_golden_registers()
437 case IP_VERSION(11, 0, 4): in gfx_v11_0_init_golden_registers()
456 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
458 amdgpu_ring_write(ring, 0); in gfx_v11_0_write_data_to_reg()
469 /* memory (1) or register (0) */ in gfx_v11_0_wait_reg_mem()
476 BUG_ON(addr0 & 0x3); /* Dword align */ in gfx_v11_0_wait_reg_mem()
494 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ in gfx_v11_ring_insert_nop()
495 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); in gfx_v11_ring_insert_nop()
497 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ in gfx_v11_ring_insert_nop()
505 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
506 uint32_t tmp = 0; in gfx_v11_0_ring_test_ring()
510 WREG32(scratch, 0xCAFEDEAD); in gfx_v11_0_ring_test_ring()
519 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
524 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
528 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_test_ring()
530 if (tmp == 0xDEADBEEF) in gfx_v11_0_ring_test_ring()
556 return 0; in gfx_v11_0_ring_test_ib()
558 memset(&ib, 0, sizeof(ib)); in gfx_v11_0_ring_test_ib()
572 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
579 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
589 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
593 ib.ptr[4] = 0xDEADBEEF; in gfx_v11_0_ring_test_ib()
601 if (r == 0) { in gfx_v11_0_ring_test_ib()
604 } else if (r < 0) { in gfx_v11_0_ring_test_ib()
608 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) in gfx_v11_0_ring_test_ib()
609 r = 0; in gfx_v11_0_ring_test_ib()
635 int err = 0; in gfx_v11_0_init_toc_microcode()
648 return 0; in gfx_v11_0_init_toc_microcode()
656 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_check_fw_cp_gfx_shadow()
657 case IP_VERSION(11, 0, 0): in gfx_v11_0_check_fw_cp_gfx_shadow()
658 case IP_VERSION(11, 0, 2): in gfx_v11_0_check_fw_cp_gfx_shadow()
659 case IP_VERSION(11, 0, 3): in gfx_v11_0_check_fw_cp_gfx_shadow()
693 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
716 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && in gfx_v11_0_init_microcode()
717 adev->pdev->revision == 0xCE) in gfx_v11_0_init_microcode()
751 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
776 u32 count = 0; in gfx_v11_0_get_csb_size()
790 return 0; in gfx_v11_0_get_csb_size()
807 u32 count = 0, i; in gfx_v11_0_get_csb_buffer()
817 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
821 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
822 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
831 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_get_csb_buffer()
840 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
845 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
848 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_get_csb_buffer()
849 buffer[count++] = cpu_to_le32(0); in gfx_v11_0_get_csb_buffer()
869 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
870 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
871 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
872 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
873 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
874 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
875 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
876 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
896 /* init spm vmid with 0xf */ in gfx_v11_0_rlc_init()
898 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v11_0_rlc_init()
900 return 0; in gfx_v11_0_rlc_init()
923 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
941 memset(hpd, 0, mec_hpd_size); in gfx_v11_0_mec_init()
947 return 0; in gfx_v11_0_mec_init()
952 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
955 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
962 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
968 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
976 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
1001 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1004 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, in gfx_v11_0_read_wave_sgprs()
1038 return 0; in gfx_v11_0_get_gfx_shadow_info()
1040 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); in gfx_v11_0_get_gfx_shadow_info()
1058 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_gpu_early_init()
1059 case IP_VERSION(11, 0, 0): in gfx_v11_0_gpu_early_init()
1060 case IP_VERSION(11, 0, 2): in gfx_v11_0_gpu_early_init()
1062 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1063 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1064 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1065 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1067 case IP_VERSION(11, 0, 3): in gfx_v11_0_gpu_early_init()
1070 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1071 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1072 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1073 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1075 case IP_VERSION(11, 0, 1): in gfx_v11_0_gpu_early_init()
1076 case IP_VERSION(11, 0, 4): in gfx_v11_0_gpu_early_init()
1077 case IP_VERSION(11, 5, 0): in gfx_v11_0_gpu_early_init()
1081 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1082 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1083 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
1084 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
1091 return 0; in gfx_v11_0_gpu_early_init()
1114 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_gfx_ring_init()
1144 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_compute_ring_init()
1158 return 0; in gfx_v11_0_compute_ring_init()
1183 uint32_t total_size = 0; in gfx_v11_0_calc_toc_total_size()
1218 return 0; in gfx_v11_0_rlc_autoload_buffer_init()
1237 if (fw_size == 0) in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1246 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1259 *(uint64_t *)fw_autoload_mask |= 0x1; in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1261 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1408 adev->sdma.instance[0].fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1409 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1416 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1432 for (pipe = 0; pipe < 2; pipe++) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1433 if (pipe==0) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1466 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); in gfx_v11_0_rlc_backdoor_autoload_enable()
1478 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1479 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1481 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v11_0_rlc_backdoor_autoload_enable()
1495 return 0; in gfx_v11_0_rlc_backdoor_autoload_enable()
1541 int i, j, k, r, ring_id = 0; in gfx_v11_0_sw_init()
1542 int xcc_id = 0; in gfx_v11_0_sw_init()
1545 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1546 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1547 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1548 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1556 case IP_VERSION(11, 0, 1): in gfx_v11_0_sw_init()
1557 case IP_VERSION(11, 0, 4): in gfx_v11_0_sw_init()
1558 case IP_VERSION(11, 5, 0): in gfx_v11_0_sw_init()
1579 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && in gfx_v11_0_sw_init()
1635 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1636 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1637 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1650 ring_id = 0; in gfx_v11_0_sw_init()
1652 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1653 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1654 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1655 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v11_0_sw_init()
1670 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); in gfx_v11_0_sw_init()
1681 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); in gfx_v11_0_sw_init()
1703 return 0; in gfx_v11_0_sw_init()
1740 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1742 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1745 amdgpu_gfx_mqd_sw_fini(adev, 0); in gfx_v11_0_sw_fini()
1748 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
1749 amdgpu_gfx_kiq_fini(adev, 0); in gfx_v11_0_sw_fini()
1766 return 0; in gfx_v11_0_sw_fini()
1774 if (instance == 0xffffffff) in gfx_v11_0_select_se_sh()
1775 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v11_0_select_se_sh()
1778 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v11_0_select_se_sh()
1781 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1787 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1793 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
1800 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1804 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1819 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1823 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1839 u32 active_rb_bitmap = 0; in gfx_v11_0_setup_rb()
1852 for (i = 0; i < max_sa; i++) { in gfx_v11_0_setup_rb()
1854 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); in gfx_v11_0_setup_rb()
1862 #define DEFAULT_SH_MEM_BASES (0x6000)
1863 #define LDS_APP_BASE 0x1
1864 #define SCRATCH_APP_BASE 0x2
1874 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1875 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1876 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v11_0_init_compute_vmid()
1883 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_init_compute_vmid()
1885 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
1886 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
1889 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1891 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
1893 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_init_compute_vmid()
1899 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1900 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1901 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1902 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1917 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1918 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1919 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1920 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1932 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1933 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
1946 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
1951 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
1954 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
1961 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { in gfx_v11_0_constants_init()
1962 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_constants_init()
1964 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
1965 if (i != 0) { in gfx_v11_0_constants_init()
1966 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v11_0_constants_init()
1970 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
1973 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_constants_init()
1984 if (me != 0) in gfx_v11_0_get_cpg_int_cntl()
1985 return 0; in gfx_v11_0_get_cpg_int_cntl()
1988 case 0: in gfx_v11_0_get_cpg_int_cntl()
1989 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
1991 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_get_cpg_int_cntl()
1993 return 0; in gfx_v11_0_get_cpg_int_cntl()
2006 return 0; in gfx_v11_0_get_cpc_int_cntl()
2009 case 0: in gfx_v11_0_get_cpc_int_cntl()
2010 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2012 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2014 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2016 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2018 return 0; in gfx_v11_0_get_cpc_int_cntl()
2031 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_enable_gui_idle_interrupt()
2032 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
2038 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2040 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2042 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2044 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2055 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v11_0_init_csb()
2057 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v11_0_init_csb()
2058 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
2059 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
2061 return 0; in gfx_v11_0_init_csb()
2066 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2068 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
2069 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
2074 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2076 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2085 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2088 /* RLC_PG_CNTL[23] = 0 (default) in gfx_v11_0_rlc_smu_handshake_cntl()
2099 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
2109 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
2118 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v11_0_rlc_enable_srm()
2121 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v11_0_rlc_enable_srm()
2135 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v11_0_load_rlcg_microcode()
2138 for (i = 0; i < fw_size; i++) in gfx_v11_0_load_rlcg_microcode()
2139 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v11_0_load_rlcg_microcode()
2142 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
2158 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2160 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2163 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2167 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2173 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2174 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2177 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2181 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2183 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v11_0_load_rlc_iram_dram_microcode()
2185 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2186 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v11_0_load_rlc_iram_dram_microcode()
2202 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2204 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2207 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2211 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2213 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v11_0_load_rlcp_rlcv_microcode()
2215 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2221 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2223 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2226 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2230 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2232 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); in gfx_v11_0_load_rlcp_rlcv_microcode()
2234 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2261 return 0; in gfx_v11_0_rlc_load_microcode()
2279 return 0; in gfx_v11_0_rlc_resume()
2285 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
2288 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
2301 return 0; in gfx_v11_0_rlc_resume()
2311 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2313 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2316 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache()
2317 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2332 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache()
2333 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2334 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache()
2335 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache()
2337 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache()
2340 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache()
2341 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_me_cache()
2342 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2345 return 0; in gfx_v11_0_config_me_cache()
2355 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2357 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2360 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache()
2361 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2376 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2377 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2378 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache()
2379 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache()
2381 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2384 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache()
2385 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_pfp_cache()
2386 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache()
2389 return 0; in gfx_v11_0_config_pfp_cache()
2399 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2402 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2405 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache()
2406 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2421 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2422 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache()
2423 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache()
2425 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2428 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2429 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_mec_cache()
2430 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache()
2433 return 0; in gfx_v11_0_config_mec_cache()
2446 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache_rs64()
2448 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache_rs64()
2451 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2452 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2453 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2454 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache_rs64()
2455 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2462 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2463 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2476 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2478 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2480 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2481 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2494 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2495 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2496 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_pfp_cache_rs64()
2499 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_pfp_cache_rs64()
2506 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2507 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2513 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2516 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2518 PFP_PIPE0_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2521 PFP_PIPE1_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2522 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2524 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_config_pfp_cache_rs64()
2526 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_config_pfp_cache_rs64()
2529 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2532 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2533 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2534 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2535 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2538 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2540 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2542 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2543 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2555 return 0; in gfx_v11_0_config_pfp_cache_rs64()
2568 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache_rs64()
2570 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
2573 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2574 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2575 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2576 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache_rs64()
2577 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2584 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2598 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2600 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2603 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2604 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2617 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2618 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2619 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2622 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_me_cache_rs64()
2629 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2630 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2636 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2639 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2641 ME_PIPE0_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2644 ME_PIPE1_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2645 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2647 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_config_me_cache_rs64()
2649 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_config_me_cache_rs64()
2652 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2655 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2656 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2657 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2658 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2661 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2663 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2665 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2666 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2678 return 0; in gfx_v11_0_config_me_cache_rs64()
2691 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2692 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2693 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache_rs64()
2694 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2695 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2697 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2698 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2699 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2700 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2703 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2704 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2706 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); in gfx_v11_0_config_mec_cache_rs64()
2707 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2710 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
2713 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_mec_cache_rs64()
2716 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
2717 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2721 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2724 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2726 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2729 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2730 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2743 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2745 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2748 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2749 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2761 return 0; in gfx_v11_0_config_mec_cache_rs64()
2779 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2780 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2781 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2784 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2787 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2790 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2793 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2796 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2797 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2798 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2801 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2802 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2803 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2806 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2809 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2812 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2815 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2818 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2819 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2820 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2823 for (pipe_id = 0; pipe_id < 4; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2824 soc21_grbm_select(adev, 1, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2825 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2828 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2831 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2834 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
2839 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2842 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2843 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2844 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2845 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2846 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2856 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2857 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v11_0_wait_for_rlc_autoload_complete()
2859 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2860 IP_VERSION(11, 0, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2861 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2862 IP_VERSION(11, 0, 4) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2863 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2864 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2865 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2)) in gfx_v11_0_wait_for_rlc_autoload_complete()
2866 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
2869 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v11_0_wait_for_rlc_autoload_complete()
2871 if ((cp_status == 0) && in gfx_v11_0_wait_for_rlc_autoload_complete()
2926 return 0; in gfx_v11_0_wait_for_rlc_autoload_complete()
2932 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_enable()
2934 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
2935 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
2936 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
2938 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_cp_gfx_enable()
2939 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
2947 return 0; in gfx_v11_0_cp_gfx_enable()
2984 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2986 for (i = 0; i < pfp_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_pfp_microcode()
2987 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2990 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2992 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode()
3056 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3058 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3061 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3062 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3063 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3064 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3065 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3072 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3073 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3086 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3088 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3090 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3091 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3104 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3105 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3106 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3109 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3116 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3117 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3123 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3126 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3128 PFP_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3131 PFP_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3132 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3134 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3136 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3139 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3142 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3143 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3144 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3145 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3148 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3150 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3152 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3153 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3165 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3202 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_me_microcode()
3204 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_me_microcode()
3205 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, in gfx_v11_0_cp_gfx_load_me_microcode()
3208 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
3210 return 0; in gfx_v11_0_cp_gfx_load_me_microcode()
3274 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3276 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3279 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3280 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3281 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3282 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3283 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3290 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3291 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3304 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3306 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3309 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3310 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3323 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3324 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3325 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3328 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3335 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3336 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3342 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3345 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3347 ME_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3350 ME_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3351 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3353 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3355 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3358 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3361 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3362 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3363 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3364 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3367 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3369 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3371 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3372 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3384 return 0; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3414 return 0; in gfx_v11_0_cp_gfx_load_microcode()
3426 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3428 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v11_0_cp_gfx_start()
3433 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3440 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3444 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3445 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3455 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_cp_gfx_start()
3462 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
3467 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3470 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3471 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3475 /* submit cs packet to copy state 0 to next available state */ in gfx_v11_0_cp_gfx_start()
3485 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3486 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3490 return 0; in gfx_v11_0_cp_gfx_start()
3498 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3501 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
3509 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_set_doorbell()
3517 DOORBELL_EN, 0); in gfx_v11_0_cp_gfx_set_doorbell()
3519 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3521 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_gfx_set_doorbell()
3523 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3525 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_gfx_set_doorbell()
3537 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v11_0_cp_gfx_resume()
3539 /* set the RB to use vmid 0 */ in gfx_v11_0_cp_gfx_resume()
3540 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
3542 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3547 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3549 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3551 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3554 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3555 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3556 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3560 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3561 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3565 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3567 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3571 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3574 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3575 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3577 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3589 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3591 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3593 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3594 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3595 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3598 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3599 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3602 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3604 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3608 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3611 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3612 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3613 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3618 /* Switch to pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3626 return 0; in gfx_v11_0_cp_gfx_resume()
3634 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3636 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3638 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3640 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3642 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3644 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3646 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3648 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3650 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3652 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3654 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3655 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
3657 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3660 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3663 MEC_ME2_HALT, 0); in gfx_v11_0_cp_compute_enable()
3668 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
3714 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3716 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v11_0_cp_compute_load_microcode()
3717 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, in gfx_v11_0_cp_compute_load_microcode()
3720 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3722 return 0; in gfx_v11_0_cp_compute_load_microcode()
3784 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3785 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3786 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3787 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3788 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3790 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3791 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3792 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3793 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3796 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3797 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3799 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3800 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3803 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
3806 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3809 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3810 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3814 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3817 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3819 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3822 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3823 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3836 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3838 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3841 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3842 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3854 return 0; in gfx_v11_0_cp_compute_load_microcode_rs64()
3863 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3864 tmp &= 0xffffff00; in gfx_v11_0_kiq_setting()
3866 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3867 tmp |= 0x80; in gfx_v11_0_kiq_setting()
3868 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3874 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3876 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3880 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3882 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3890 bool priority = 0; in gfx_v11_0_gfx_mqd_set_priority()
3894 * 0x0 = low priority, 0x1 = high priority in gfx_v11_0_gfx_mqd_set_priority()
3899 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); in gfx_v11_0_gfx_mqd_set_priority()
3913 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
3914 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
3917 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3921 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v11_0_gfx_mqd_init()
3922 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3924 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); in gfx_v11_0_gfx_mqd_init()
3927 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ in gfx_v11_0_gfx_mqd_init()
3928 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); in gfx_v11_0_gfx_mqd_init()
3929 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3930 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
3936 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); in gfx_v11_0_gfx_mqd_init()
3947 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3949 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
3953 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3954 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
3958 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); in gfx_v11_0_gfx_mqd_init()
3967 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_gfx_mqd_init()
3975 DOORBELL_EN, 0); in gfx_v11_0_gfx_mqd_init()
3979 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
3984 return 0; in gfx_v11_0_gfx_mqd_init()
3991 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_kgq_init_queue()
3994 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
3996 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kgq_init_queue()
3998 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kgq_init_queue()
4007 ring->wptr = 0; in gfx_v11_0_kgq_init_queue()
4008 *ring->wptr_cpu_addr = 0; in gfx_v11_0_kgq_init_queue()
4012 return 0; in gfx_v11_0_kgq_init_queue()
4020 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
4024 if (unlikely(r != 0)) in gfx_v11_0_cp_async_gfx_ring_resume()
4038 r = amdgpu_gfx_enable_kgq(adev, 0); in gfx_v11_0_cp_async_gfx_ring_resume()
4052 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
4053 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
4054 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4055 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4056 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4057 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4058 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
4065 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); in gfx_v11_0_compute_mqd_init()
4072 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4080 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4082 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4085 DOORBELL_EN, 0); in gfx_v11_0_compute_mqd_init()
4091 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
4092 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
4093 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
4094 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
4097 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4100 /* set MQD vmid to 0 */ in gfx_v11_0_compute_mqd_init()
4101 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in gfx_v11_0_compute_mqd_init()
4102 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()
4111 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
4125 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4127 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4131 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4132 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4134 tmp = 0; in gfx_v11_0_compute_mqd_init()
4137 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4144 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4146 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4152 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
4155 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
4157 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); in gfx_v11_0_compute_mqd_init()
4158 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); in gfx_v11_0_compute_mqd_init()
4162 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); in gfx_v11_0_compute_mqd_init()
4172 return 0; in gfx_v11_0_compute_mqd_init()
4183 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4186 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4189 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4191 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4195 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
4199 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4203 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4204 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
4205 for (j = 0; j < adev->usec_timeout; j++) { in gfx_v11_0_kiq_init_register()
4206 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4210 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
4212 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
4214 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4216 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4221 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4223 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4226 /* set MQD vmid to 0 */ in gfx_v11_0_kiq_init_register()
4227 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
4231 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
4233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v11_0_kiq_init_register()
4237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
4241 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
4243 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v11_0_kiq_init_register()
4247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
4249 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
4254 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_kiq_init_register()
4256 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_kiq_init_register()
4260 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4264 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4266 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4270 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4272 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v11_0_kiq_init_register()
4276 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
4280 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
4282 return 0; in gfx_v11_0_kiq_init_register()
4294 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4295 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4298 ring->wptr = 0; in gfx_v11_0_kiq_init_queue()
4302 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4304 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4307 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4311 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4314 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4317 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4318 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4321 return 0; in gfx_v11_0_kiq_init_queue()
4328 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4331 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4333 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kcq_init_queue()
4335 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kcq_init_queue()
4345 ring->wptr = 0; in gfx_v11_0_kcq_init_queue()
4346 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); in gfx_v11_0_kcq_init_queue()
4350 return 0; in gfx_v11_0_kcq_init_queue()
4358 ring = &adev->gfx.kiq[0].ring; in gfx_v11_0_kiq_resume()
4361 if (unlikely(r != 0)) in gfx_v11_0_kiq_resume()
4365 if (unlikely(r != 0)) { in gfx_v11_0_kiq_resume()
4375 return 0; in gfx_v11_0_kiq_resume()
4381 int r = 0, i; in gfx_v11_0_kcq_resume()
4386 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4390 if (unlikely(r != 0)) in gfx_v11_0_kcq_resume()
4403 r = amdgpu_gfx_enable_kcq(adev, 0); in gfx_v11_0_kcq_resume()
4458 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4465 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4472 return 0; in gfx_v11_0_cp_resume()
4498 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); in gfx_v11_0_gfxhub_enable()
4500 return 0; in gfx_v11_0_gfxhub_enable()
4509 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); in gfx_v11_0_select_cp_fw_arch()
4511 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4513 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); in gfx_v11_0_select_cp_fw_arch()
4515 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4526 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4527 if (gb_addr_config == 0) in get_gb_addr_config()
4555 return 0; in get_gb_addr_config()
4562 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4564 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4566 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4568 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4588 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4663 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); in gfx_v11_0_hw_init()
4672 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4673 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4674 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_hw_fini()
4678 if (amdgpu_gfx_disable_kgq(adev, 0)) in gfx_v11_0_hw_fini()
4682 if (amdgpu_gfx_disable_kcq(adev, 0)) in gfx_v11_0_hw_fini()
4694 return 0; in gfx_v11_0_hw_fini()
4703 return 0; in gfx_v11_0_hw_fini()
4720 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v11_0_is_idle()
4733 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_idle()
4735 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v11_0_wait_for_idle()
4739 return 0; in gfx_v11_0_wait_for_idle()
4750 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_request_gfx_index_mutex()
4751 /* Request with MeId=2, PipeId=0 */ in gfx_v11_0_request_gfx_index_mutex()
4752 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); in gfx_v11_0_request_gfx_index_mutex()
4754 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); in gfx_v11_0_request_gfx_index_mutex()
4756 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); in gfx_v11_0_request_gfx_index_mutex()
4774 return 0; in gfx_v11_0_request_gfx_index_mutex()
4779 u32 grbm_soft_reset = 0; in gfx_v11_0_soft_reset()
4784 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4786 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4787 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4788 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4789 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4790 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4791 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4794 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4795 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4796 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4797 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4799 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
4800 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
4804 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4805 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4806 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4807 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4809 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); in gfx_v11_0_soft_reset()
4813 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_soft_reset()
4825 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
4828 // to get sufficient time for GFX_HQD_ACTIVE reach 0 in gfx_v11_0_soft_reset()
4829 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4830 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4831 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4841 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4842 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
4843 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) in gfx_v11_0_soft_reset()
4853 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4864 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4866 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4868 SOFT_RESET_CP, 0); in gfx_v11_0_soft_reset()
4870 SOFT_RESET_GFX, 0); in gfx_v11_0_soft_reset()
4872 SOFT_RESET_CPF, 0); in gfx_v11_0_soft_reset()
4874 SOFT_RESET_CPC, 0); in gfx_v11_0_soft_reset()
4876 SOFT_RESET_CPG, 0); in gfx_v11_0_soft_reset()
4877 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4879 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); in gfx_v11_0_soft_reset()
4880 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); in gfx_v11_0_soft_reset()
4881 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); in gfx_v11_0_soft_reset()
4883 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); in gfx_v11_0_soft_reset()
4884 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
4886 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4887 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
4892 printk("Failed to wait CP_VMID_RESET to 0\n"); in gfx_v11_0_soft_reset()
4896 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4901 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4903 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4915 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4922 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
4948 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
4949 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
4950 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
4952 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
4957 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
4958 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
4959 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
4961 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
4978 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
4979 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
4983 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
4984 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
4988 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
4989 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
4993 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
4994 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5026 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
5030 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5034 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_late_init()
5037 return 0; in gfx_v11_0_late_init()
5045 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
5057 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v11_0_set_safe_mode()
5060 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_set_safe_mode()
5061 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v11_0_set_safe_mode()
5070 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
5081 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_perf_clk()
5089 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_perf_clk()
5100 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_sram_fgcg()
5108 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_sram_fgcg()
5119 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_repeater_fgcg()
5127 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_repeater_fgcg()
5142 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5149 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5153 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5160 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5178 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_coarse_grain_clock_gating()
5191 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5193 /* enable cgcg FSM(0x0000363F) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5194 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5198 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5204 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5209 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5212 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5216 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5222 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5227 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5229 /* set IDLE_POLL_COUNT(0x00900100) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5230 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5233 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5234 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v11_0_update_coarse_grain_clock_gating()
5237 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5239 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5244 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5246 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5248 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5252 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5254 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5258 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5267 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5270 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5278 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5280 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5282 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5286 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5288 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5296 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5316 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5318 return 0; in gfx_v11_0_update_gfx_clock_gating()
5326 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
5337 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5339 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5368 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5375 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
5379 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_cntl_power_gating()
5380 case IP_VERSION(11, 0, 1): in gfx_v11_cntl_power_gating()
5381 case IP_VERSION(11, 0, 4): in gfx_v11_cntl_power_gating()
5382 case IP_VERSION(11, 5, 0): in gfx_v11_cntl_power_gating()
5385 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); in gfx_v11_cntl_power_gating()
5395 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5399 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5409 return 0; in gfx_v11_0_set_powergating_state()
5411 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_powergating_state()
5412 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_powergating_state()
5413 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_powergating_state()
5414 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_powergating_state()
5417 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_powergating_state()
5418 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_powergating_state()
5419 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_powergating_state()
5435 return 0; in gfx_v11_0_set_powergating_state()
5444 return 0; in gfx_v11_0_set_clockgating_state()
5446 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_clockgating_state()
5447 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_clockgating_state()
5448 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_clockgating_state()
5449 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_clockgating_state()
5450 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_clockgating_state()
5451 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_clockgating_state()
5452 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_clockgating_state()
5462 return 0; in gfx_v11_0_set_clockgating_state()
5471 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_get_clockgating_state()
5488 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
5497 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
5521 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5522 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5538 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
5540 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
5594 reg_mem_engine = 0; in gfx_v11_0_ring_emit_hdp_flush()
5600 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, in gfx_v11_0_ring_emit_hdp_flush()
5603 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
5612 u32 header, control = 0; in gfx_v11_0_ring_emit_ib_gfx()
5633 control |= 0x400000; in gfx_v11_0_ring_emit_ib_gfx()
5636 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_gfx()
5639 (2 << 0) | in gfx_v11_0_ring_emit_ib_gfx()
5656 control |= 0x40000000; in gfx_v11_0_ring_emit_ib_compute()
5666 * GDS to 0 for this ring (me/pipe). in gfx_v11_0_ring_emit_ib_compute()
5675 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_compute()
5678 (2 << 0) | in gfx_v11_0_ring_emit_ib_compute()
5701 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
5708 BUG_ON(addr & 0x7); in gfx_v11_0_ring_emit_fence()
5710 BUG_ON(addr & 0x3); in gfx_v11_0_ring_emit_fence()
5716 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); in gfx_v11_0_ring_emit_fence()
5725 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), in gfx_v11_0_ring_emit_pipeline_sync()
5726 upper_32_bits(addr), seq, 0xffffffff, 4); in gfx_v11_0_ring_emit_pipeline_sync()
5733 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v11_0_ring_invalidate_tlbs()
5745 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); in gfx_v11_0_ring_emit_vm_flush()
5752 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v11_0_ring_emit_vm_flush()
5753 amdgpu_ring_write(ring, 0x0); in gfx_v11_0_ring_emit_vm_flush()
5759 ring->set_q_mode_offs = 0; in gfx_v11_0_ring_emit_vm_flush()
5773 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5782 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5783 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5784 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()
5785 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_fence_kiq()
5786 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ in gfx_v11_0_ring_emit_fence_kiq()
5793 uint32_t dw2 = 0; in gfx_v11_0_ring_emit_cntxcntl()
5795 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v11_0_ring_emit_cntxcntl()
5798 dw2 |= 0x8001; in gfx_v11_0_ring_emit_cntxcntl()
5800 dw2 |= 0x01000000; in gfx_v11_0_ring_emit_cntxcntl()
5802 dw2 |= 0x10002; in gfx_v11_0_ring_emit_cntxcntl()
5807 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_cntxcntl()
5818 /* discard following DWs if *cond_exec_gpu_addr==0 */ in gfx_v11_0_ring_emit_init_cond_exec()
5819 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5822 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5858 amdgpu_ring_write(ring, shadow_va ? 1 : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5859 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_gfx_shadow()
5882 amdgpu_ring_write(ring, 0x1); in gfx_v11_0_ring_emit_gfx_shadow()
5893 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5895 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5908 *ring->set_q_mode_ptr = 0; in gfx_v11_0_ring_emit_gfx_shadow()
5920 int i, r = 0; in gfx_v11_0_ring_preempt_ib()
5922 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v11_0_ring_preempt_ib()
5951 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_preempt_ib()
5971 struct v10_de_ib_state de_payload = {0}; in gfx_v11_0_ring_emit_de_meta()
5978 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
5986 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
6007 WRITE_DATA_CACHE_POLICY(0)); in gfx_v11_0_ring_emit_de_meta()
6022 uint32_t v = secure ? FRAME_TMZ : 0; in gfx_v11_0_ring_emit_frame_cntl()
6024 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); in gfx_v11_0_ring_emit_frame_cntl()
6025 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); in gfx_v11_0_ring_emit_frame_cntl()
6034 amdgpu_ring_write(ring, 0 | /* src: register*/ in gfx_v11_0_ring_emit_rreg()
6038 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_rreg()
6048 uint32_t cmd = 0; in gfx_v11_0_ring_emit_wreg()
6064 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_wreg()
6071 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); in gfx_v11_0_ring_emit_reg_wait()
6080 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, in gfx_v11_0_ring_emit_reg_write_reg_wait()
6081 ref, mask, 0x20); in gfx_v11_0_ring_emit_reg_write_reg_wait()
6088 uint32_t value = 0; in gfx_v11_0_ring_soft_recovery()
6090 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v11_0_ring_soft_recovery()
6091 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v11_0_ring_soft_recovery()
6094 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6095 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v11_0_ring_soft_recovery()
6096 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6108 case 0: in gfx_v11_0_set_gfx_eop_interrupt_state()
6109 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6112 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6127 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6129 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6159 case 0: in gfx_v11_0_set_compute_eop_interrupt_state()
6160 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6163 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6166 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6169 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6184 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6186 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6209 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6212 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); in gfx_v11_0_set_eop_interrupt_state()
6215 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6229 return 0; in gfx_v11_0_set_eop_interrupt_state()
6239 uint32_t mes_queue_id = entry->src_data[0]; in gfx_v11_0_eop_irq()
6256 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_eop_irq()
6257 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_eop_irq()
6258 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_eop_irq()
6261 case 0: in gfx_v11_0_eop_irq()
6262 if (pipe_id == 0) in gfx_v11_0_eop_irq()
6263 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
6269 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
6284 return 0; in gfx_v11_0_eop_irq()
6298 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6299 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6306 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6311 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6312 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6320 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6330 return 0; in gfx_v11_0_set_priv_reg_fault_state()
6344 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_bad_op_fault_state()
6345 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
6352 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6357 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6358 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_bad_op_fault_state()
6366 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6375 return 0; in gfx_v11_0_set_bad_op_fault_state()
6389 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_inst_fault_state()
6390 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_inst_fault_state()
6397 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
6407 return 0; in gfx_v11_0_set_priv_inst_fault_state()
6417 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_handle_priv_fault()
6418 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_handle_priv_fault()
6419 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_handle_priv_fault()
6422 case 0: in gfx_v11_0_handle_priv_fault()
6423 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
6432 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
6451 return 0; in gfx_v11_0_priv_reg_irq()
6460 return 0; in gfx_v11_0_bad_op_irq()
6469 return 0; in gfx_v11_0_priv_inst_irq()
6479 return 0; in gfx_v11_0_rlc_gc_fed_irq()
6482 #if 0
6489 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6491 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6497 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6499 GENERIC2_INT_ENABLE, 0);
6500 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6504 GENERIC2_INT_ENABLE, 0);
6507 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6510 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6522 return 0;
6540 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ in gfx_v11_0_emit_mem_sync()
6541 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v11_0_emit_mem_sync()
6542 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx_v11_0_emit_mem_sync()
6543 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v11_0_emit_mem_sync()
6544 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v11_0_emit_mem_sync()
6545 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ in gfx_v11_0_emit_mem_sync()
6562 if (unlikely(r != 0)) { in gfx_v11_0_reset_kgq()
6590 int i, r = 0; in gfx_v11_0_reset_kcq()
6595 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_reset_kcq()
6597 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_reset_kcq()
6598 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_reset_kcq()
6599 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_reset_kcq()
6602 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_reset_kcq()
6603 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_reset_kcq()
6609 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_reset_kcq()
6611 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_reset_kcq()
6618 if (unlikely(r != 0)) { in gfx_v11_0_reset_kcq()
6645 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_print()
6651 for (i = 0; i < reg_count; i++) in gfx_v11_ip_print()
6652 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6666 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
6667 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_print()
6668 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6670 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6671 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6684 index = 0; in gfx_v11_ip_print()
6691 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_print()
6692 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
6693 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6695 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6696 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6709 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_dump()
6716 for (i = 0; i < reg_count; i++) in gfx_v11_ip_dump()
6727 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_dump()
6728 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_dump()
6729 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6731 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v11_ip_dump()
6732 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6741 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6749 index = 0; in gfx_v11_ip_dump()
6753 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_dump()
6754 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_dump()
6755 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6756 soc21_grbm_select(adev, i, j, k, 0); in gfx_v11_ip_dump()
6758 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6767 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6796 .align_mask = 0xff,
6797 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6848 .align_mask = 0xff,
6849 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6886 .align_mask = 0xff,
6887 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6917 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6919 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6922 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
6964 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ in gfx_v11_0_set_irq_funcs()
6990 adev->gds.gds_size = 0x1000; in gfx_v11_0_set_gds_init()
7021 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
7027 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7028 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7045 cu_active_bitmap = 0; in gfx_v11_0_get_cu_active_bitmap_per_sh()
7047 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { in gfx_v11_0_get_cu_active_bitmap_per_sh()
7060 int i, j, k, counter, active_cu_number = 0; in gfx_v11_0_get_cu_info()
7070 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
7071 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7076 counter = 0; in gfx_v11_0_get_cu_info()
7077 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7089 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} in gfx_v11_0_get_cu_info()
7090 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} in gfx_v11_0_get_cu_info()
7091 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} in gfx_v11_0_get_cu_info()
7092 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} in gfx_v11_0_get_cu_info()
7093 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} in gfx_v11_0_get_cu_info()
7098 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; in gfx_v11_0_get_cu_info()
7100 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()
7109 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7115 return 0; in gfx_v11_0_get_cu_info()
7122 .minor = 0,
7123 .rev = 0,