201 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v6_0_page_flip()
204 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
207 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
209 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
213 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v6_0_page_flip()
474 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_fmt()
977 	arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
981 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
982 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
986 	tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
989 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
990 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
994 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);  in dce_v6_0_program_watermarks()
997 	WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);  in dce_v6_0_program_watermarks()
998 	WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);  in dce_v6_0_program_watermarks()
1042 	WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,  in dce_v6_0_line_buffer_adjust()
1823 	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);  in dce_v6_0_grph_enable()
1983 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1985 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1987 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1989 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1991 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1993 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_crtc_do_set_base()
1994 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v6_0_crtc_do_set_base()
2001 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2008 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2009 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2010 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2011 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2012 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v6_0_crtc_do_set_base()
2013 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v6_0_crtc_do_set_base()
2016 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v6_0_crtc_do_set_base()
2020 	WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2024 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2029 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2033 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2059 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v6_0_set_interleave()
2062 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_set_interleave()
2076 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2079 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2081 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2083 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2087 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2089 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2090 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2091 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2093 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2094 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2095 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2097 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2098 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v6_0_crtc_load_lut()
2100 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2105 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2111 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2116 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2119 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2122 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2126 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2203 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v6_0_lock_cursor()
2208 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v6_0_lock_cursor()
2216 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_hide_cursor()
2228 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2230 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2233 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2266 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v6_0_cursor_move_locked()
2267 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v6_0_cursor_move_locked()
2268 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_cursor_move_locked()
2625 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v6_0_crtc_init()