Lines Matching +full:hpd +full:- +full:pin
72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
87 (0x13830 - 0x7030) >> 2,
94 uint32_t hpd; member
100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
156 if (crtc >= adev->mode_info.num_crtc) in dce_v6_0_vblank_get_counter()
167 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_init()
168 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_init()
176 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_fini()
177 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_fini()
181 * dce_v6_0_page_flip - pageflip callback.
197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
205 fb->pitches[0] / fb->format->cpp[0]); in dce_v6_0_page_flip()
207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v6_0_crtc_get_scanoutpos()
220 return -EINVAL; in dce_v6_0_crtc_get_scanoutpos()
229 * dce_v6_0_hpd_sense - hpd sense callback.
232 * @hpd: hpd (hotplug detect) pin
238 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_sense() argument
242 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_sense()
245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) in dce_v6_0_hpd_sense()
252 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
255 * @hpd: hpd (hotplug detect) pin
257 * Set the polarity of the hpd pin (evergreen+).
260 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_set_polarity() argument
263 bool connected = dce_v6_0_hpd_sense(adev, hpd); in dce_v6_0_hpd_set_polarity()
265 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_set_polarity()
268 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
277 int hpd) in dce_v6_0_hpd_int_ack() argument
281 if (hpd >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_int_ack()
282 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v6_0_hpd_int_ack()
286 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_int_ack()
288 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_int_ack()
292 * dce_v6_0_hpd_init - hpd setup callback.
296 * Setup the hpd pins used by the card (evergreen+).
297 * Enable the pin, set the polarity, and enable the hpd interrupts.
310 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_init()
313 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
315 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
317 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v6_0_hpd_init()
318 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v6_0_hpd_init()
319 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v6_0_hpd_init()
324 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
326 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
330 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
331 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
332 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
338 * dce_v6_0_hpd_fini - hpd tear down callback.
342 * Tear down the hpd pins used by the card (evergreen+).
343 * Disable the hpd interrupts.
356 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_fini()
359 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_fini()
361 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_fini()
363 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_fini()
384 switch (adev->asic_type) { in dce_v6_0_get_num_crtc()
423 struct drm_device *dev = encoder->dev; in dce_v6_0_program_fmt()
427 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt()
435 dither = amdgpu_connector->dither; in dce_v6_0_program_fmt()
439 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v6_0_program_fmt()
474 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
478 * si_get_number_of_dram_channels - get the number of dram channels
515 u32 yclk; /* bandwidth per dram data pin in kHz */
530 * dce_v6_0_dram_bandwidth - get the dram bandwidth
546 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()
548 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()
559 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
575 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()
577 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()
588 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
604 sclk.full = dfixed_const(wm->sclk); in dce_v6_0_data_return_bandwidth()
617 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
633 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
648 * dce_v6_0_available_bandwidth - get the min available bandwidth
667 * dce_v6_0_average_bandwidth - get the average available bandwidth
688 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v6_0_average_bandwidth()
690 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v6_0_average_bandwidth()
691 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
693 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
700 * dce_v6_0_latency_watermark - get the latency watermark
715 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v6_0_latency_watermark()
716 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
717 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
723 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
728 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
729 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
730 (wm->vtaps >= 5) || in dce_v6_0_latency_watermark()
731 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
737 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
739 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v6_0_latency_watermark()
742 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v6_0_latency_watermark()
744 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
751 if (line_fill_time < wm->active_time) in dce_v6_0_latency_watermark()
754 return latency + (line_fill_time - wm->active_time); in dce_v6_0_latency_watermark()
759 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
772 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
779 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
792 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
799 * dce_v6_0_check_latency_hiding - check latency hiding
809 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
810 u32 line_time = wm->active_time + wm->blank_time; in dce_v6_0_check_latency_hiding()
816 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
819 if (lb_partitions <= (wm->vtaps + 1)) in dce_v6_0_check_latency_hiding()
825 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v6_0_check_latency_hiding()
834 * dce_v6_0_program_watermarks - program display watermarks
848 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
860 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
861 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v6_0_program_watermarks()
862 (u32)mode->clock); in dce_v6_0_program_watermarks()
863 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v6_0_program_watermarks()
864 (u32)mode->clock); in dce_v6_0_program_watermarks()
872 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
878 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
879 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
882 wm_high.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
883 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
885 wm_high.blank_time = line_time - wm_high.active_time; in dce_v6_0_program_watermarks()
887 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
889 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
891 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
898 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
905 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
906 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
909 wm_low.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
910 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
912 wm_low.blank_time = line_time - wm_low.active_time; in dce_v6_0_program_watermarks()
914 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
916 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
918 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
935 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
943 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
950 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
954 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
962 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
966 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
973 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
977 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
981 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
982 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
986 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
989 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
990 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
994 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
997 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
998 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
1001 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
1002 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
1005 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
1015 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1022 * 0 - half lb in dce_v6_0_line_buffer_adjust()
1023 * 2 - whole lb, other crtc must be disabled in dce_v6_0_line_buffer_adjust()
1027 * non-linked crtcs for maximum line buffer allocation. in dce_v6_0_line_buffer_adjust()
1029 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1042 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1047 for (i = 0; i < adev->usec_timeout; i++) { in dce_v6_0_line_buffer_adjust()
1054 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1070 * dce_v6_0_bandwidth_update - program display watermarks
1084 if (!adev->mode_info.mode_config_initialized) in dce_v6_0_bandwidth_update()
1089 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_bandwidth_update()
1090 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1093 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { in dce_v6_0_bandwidth_update()
1094 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1095 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1096 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1097 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1098 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1099 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1108 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_connected_pins()
1109 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, in dce_v6_0_audio_get_connected_pins()
1113 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_get_connected_pins()
1115 adev->mode_info.audio.pin[i].connected = true; in dce_v6_0_audio_get_connected_pins()
1126 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_pin()
1127 if (adev->mode_info.audio.pin[i].connected) in dce_v6_0_audio_get_pin()
1128 return &adev->mode_info.audio.pin[i]; in dce_v6_0_audio_get_pin()
1136 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_audio_select_pin()
1138 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_select_pin()
1140 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v6_0_audio_select_pin()
1143 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce_v6_0_audio_select_pin()
1145 dig->afmt->pin->id)); in dce_v6_0_audio_select_pin()
1151 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_latency_fields()
1154 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_latency_fields()
1163 if (connector->encoder == encoder) { in dce_v6_0_audio_write_latency_fields()
1175 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_audio_write_latency_fields()
1178 if (connector->latency_present[interlace]) { in dce_v6_0_audio_write_latency_fields()
1180 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1182 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1189 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_latency_fields()
1195 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_speaker_allocation()
1198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_speaker_allocation()
1208 if (connector->encoder == encoder) { in dce_v6_0_audio_write_speaker_allocation()
1220 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); in dce_v6_0_audio_write_speaker_allocation()
1227 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1234 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) in dce_v6_0_audio_write_speaker_allocation()
1248 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1256 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_sad_regs()
1259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_sad_regs()
1283 if (connector->encoder == encoder) { in dce_v6_0_audio_write_sad_regs()
1295 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); in dce_v6_0_audio_write_sad_regs()
1304 int max_channels = -1; in dce_v6_0_audio_write_sad_regs()
1310 if (sad->format == eld_reg_to_type[i][1]) { in dce_v6_0_audio_write_sad_regs()
1311 if (sad->channels > max_channels) { in dce_v6_0_audio_write_sad_regs()
1313 MAX_CHANNELS, sad->channels); in dce_v6_0_audio_write_sad_regs()
1315 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v6_0_audio_write_sad_regs()
1317 SUPPORTED_FREQUENCIES, sad->freq); in dce_v6_0_audio_write_sad_regs()
1318 max_channels = sad->channels; in dce_v6_0_audio_write_sad_regs()
1321 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v6_0_audio_write_sad_regs()
1322 stereo_freqs |= sad->freq; in dce_v6_0_audio_write_sad_regs()
1330 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v6_0_audio_write_sad_regs()
1338 struct amdgpu_audio_pin *pin, in dce_v6_0_audio_enable() argument
1341 if (!pin) in dce_v6_0_audio_enable()
1344 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v6_0_audio_enable()
1350 (0x1780 - 0x1780),
1351 (0x1786 - 0x1780),
1352 (0x178c - 0x1780),
1353 (0x1792 - 0x1780),
1354 (0x1798 - 0x1780),
1355 (0x179d - 0x1780),
1356 (0x17a4 - 0x1780),
1366 adev->mode_info.audio.enabled = true; in dce_v6_0_audio_init()
1368 switch (adev->asic_type) { in dce_v6_0_audio_init()
1373 adev->mode_info.audio.num_pins = 6; in dce_v6_0_audio_init()
1376 adev->mode_info.audio.num_pins = 2; in dce_v6_0_audio_init()
1380 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_init()
1381 adev->mode_info.audio.pin[i].channels = -1; in dce_v6_0_audio_init()
1382 adev->mode_info.audio.pin[i].rate = -1; in dce_v6_0_audio_init()
1383 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v6_0_audio_init()
1384 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v6_0_audio_init()
1385 adev->mode_info.audio.pin[i].category_code = 0; in dce_v6_0_audio_init()
1386 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_init()
1387 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v6_0_audio_init()
1388 adev->mode_info.audio.pin[i].id = i; in dce_v6_0_audio_init()
1389 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_init()
1402 if (!adev->mode_info.audio.enabled) in dce_v6_0_audio_fini()
1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v6_0_audio_fini()
1406 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_fini()
1408 adev->mode_info.audio.enabled = false; in dce_v6_0_audio_fini()
1413 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_vbi_packet()
1416 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_vbi_packet()
1419 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_vbi_packet()
1423 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_vbi_packet()
1429 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_acr()
1433 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_acr()
1436 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1440 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1442 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1444 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1445 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1447 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1449 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1451 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1452 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1454 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1456 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1458 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1459 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1461 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1467 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_avi_infoframe()
1470 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_avi_infoframe()
1491 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1493 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1495 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1497 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1500 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_set_avi_infoframe()
1504 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_avi_infoframe()
1509 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_dto()
1511 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto()
1523 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1543 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_packet()
1546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_packet()
1549 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1551 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1553 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1555 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1557 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1559 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1561 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1568 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1570 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1572 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1574 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1577 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1579 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1582 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1587 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_mute()
1590 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_mute()
1593 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); in dce_v6_0_audio_set_mute()
1595 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); in dce_v6_0_audio_set_mute()
1600 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_hdmi_enable()
1603 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_hdmi_enable()
1607 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1612 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1614 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1616 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1618 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1620 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1622 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1627 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1629 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1631 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1637 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_dp_enable()
1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_dp_enable()
1644 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1646 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1648 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1650 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1652 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1657 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1659 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); in dce_v6_0_audio_dp_enable()
1666 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_setmode()
1669 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_setmode()
1676 if (!dig || !dig->afmt) in dce_v6_0_afmt_setmode()
1681 if (connector->encoder == encoder) { in dce_v6_0_afmt_setmode()
1693 if (!dig->afmt->enabled) in dce_v6_0_afmt_setmode()
1696 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); in dce_v6_0_afmt_setmode()
1697 if (!dig->afmt->pin) in dce_v6_0_afmt_setmode()
1700 if (encoder->crtc) { in dce_v6_0_afmt_setmode()
1701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode()
1702 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1706 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_setmode()
1713 dce_v6_0_audio_set_dto(encoder, mode->clock); in dce_v6_0_afmt_setmode()
1715 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); in dce_v6_0_afmt_setmode()
1717 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); in dce_v6_0_afmt_setmode()
1730 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); in dce_v6_0_afmt_setmode()
1735 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_enable()
1738 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_enable()
1740 if (!dig || !dig->afmt) in dce_v6_0_afmt_enable()
1744 if (enable && dig->afmt->enabled) in dce_v6_0_afmt_enable()
1747 if (!enable && !dig->afmt->enabled) in dce_v6_0_afmt_enable()
1750 if (!enable && dig->afmt->pin) { in dce_v6_0_afmt_enable()
1751 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_enable()
1752 dig->afmt->pin = NULL; in dce_v6_0_afmt_enable()
1755 dig->afmt->enabled = enable; in dce_v6_0_afmt_enable()
1758 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v6_0_afmt_enable()
1765 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v6_0_afmt_init()
1766 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_init()
1769 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_init()
1770 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v6_0_afmt_init()
1771 if (adev->mode_info.afmt[i]) { in dce_v6_0_afmt_init()
1772 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v6_0_afmt_init()
1773 adev->mode_info.afmt[i]->id = i; in dce_v6_0_afmt_init()
1776 kfree(adev->mode_info.afmt[j]); in dce_v6_0_afmt_init()
1777 adev->mode_info.afmt[j] = NULL; in dce_v6_0_afmt_init()
1780 return -ENOMEM; in dce_v6_0_afmt_init()
1790 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_fini()
1791 kfree(adev->mode_info.afmt[i]); in dce_v6_0_afmt_fini()
1792 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_fini()
1809 struct drm_device *dev = crtc->dev; in dce_v6_0_vga_enable()
1813 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1814 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1820 struct drm_device *dev = crtc->dev; in dce_v6_0_grph_enable()
1823 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1831 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_do_set_base()
1844 if (!atomic && !crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
1852 target_fb = crtc->primary->fb; in dce_v6_0_crtc_do_set_base()
1857 obj = target_fb->obj[0]; in dce_v6_0_crtc_do_set_base()
1864 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v6_0_crtc_do_set_base()
1868 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1876 switch (target_fb->format->format) { in dce_v6_0_crtc_do_set_base()
1927 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1937 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1952 &target_fb->format->format); in dce_v6_0_crtc_do_set_base()
1953 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1983 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1985 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1987 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1989 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1991 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1993 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
1994 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
2001 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2008 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2009 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2010 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2011 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2012 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
2013 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
2015 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v6_0_crtc_do_set_base()
2016 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2020 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2021 target_fb->height); in dce_v6_0_crtc_do_set_base()
2024 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2026 viewport_w = crtc->mode.hdisplay; in dce_v6_0_crtc_do_set_base()
2027 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v6_0_crtc_do_set_base()
2029 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2033 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2035 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
2036 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v6_0_crtc_do_set_base()
2054 struct drm_device *dev = crtc->dev; in dce_v6_0_set_interleave()
2058 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_set_interleave()
2059 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2062 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2069 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_load_lut()
2074 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2076 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2079 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2081 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2083 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2087 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2089 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2090 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2091 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2093 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2094 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2095 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2097 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2098 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2100 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2101 r = crtc->gamma_store; in dce_v6_0_crtc_load_lut()
2102 g = r + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2103 b = g + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2105 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2111 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2116 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2119 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2122 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2126 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2134 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_pick_dig_encoder()
2136 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_pick_dig_encoder()
2138 return dig->linkb ? 1 : 0; in dce_v6_0_pick_dig_encoder()
2140 return dig->linkb ? 3 : 2; in dce_v6_0_pick_dig_encoder()
2142 return dig->linkb ? 5 : 4; in dce_v6_0_pick_dig_encoder()
2146 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v6_0_pick_dig_encoder()
2152 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2157 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2169 struct drm_device *dev = crtc->dev; in dce_v6_0_pick_pll()
2174 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2175 if (adev->clock.dp_extclk) in dce_v6_0_pick_pll()
2199 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_lock_cursor()
2203 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2208 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2214 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_hide_cursor()
2216 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2226 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_show_cursor()
2228 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2229 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2230 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2231 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2233 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2244 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_cursor_move_locked()
2247 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2249 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2250 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2253 x += crtc->x; in dce_v6_0_cursor_move_locked()
2254 y += crtc->y; in dce_v6_0_cursor_move_locked()
2255 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v6_0_cursor_move_locked()
2258 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2262 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2266 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2267 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2268 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2269 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2306 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2307 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2309 return -EINVAL; in dce_v6_0_crtc_cursor_set2()
2314 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2315 return -ENOENT; in dce_v6_0_crtc_cursor_set2()
2325 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v6_0_crtc_cursor_set2()
2329 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); in dce_v6_0_crtc_cursor_set2()
2333 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2337 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2338 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2339 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2340 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2343 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2344 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2348 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2349 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2350 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2351 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2358 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2359 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2365 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2368 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2376 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2379 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2380 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2419 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_dpms()
2426 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2431 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2432 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v6_0_crtc_dpms()
2433 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v6_0_crtc_dpms()
2441 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2444 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2469 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_disable()
2475 if (crtc->primary->fb) { in dce_v6_0_crtc_disable()
2479 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v6_0_crtc_disable()
2493 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_crtc_disable()
2494 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2495 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
2496 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2497 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2505 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2509 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2516 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2517 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2518 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2519 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2529 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2530 return -EINVAL; in dce_v6_0_crtc_mode_set()
2539 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2550 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_mode_fixup()
2554 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_crtc_mode_fixup()
2555 if (encoder->crtc == crtc) { in dce_v6_0_crtc_mode_fixup()
2556 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2557 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2561 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2562 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2563 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2571 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2572 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
2573 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2574 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2612 return -ENOMEM; in dce_v6_0_crtc_init()
2614 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2616 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2617 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2618 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2620 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2621 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2622 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2623 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2625 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2627 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2628 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2629 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2630 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2631 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
2640 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; in dce_v6_0_early_init()
2641 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; in dce_v6_0_early_init()
2645 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); in dce_v6_0_early_init()
2647 switch (adev->asic_type) { in dce_v6_0_early_init()
2651 adev->mode_info.num_hpd = 6; in dce_v6_0_early_init()
2652 adev->mode_info.num_dig = 6; in dce_v6_0_early_init()
2655 adev->mode_info.num_hpd = 2; in dce_v6_0_early_init()
2656 adev->mode_info.num_dig = 2; in dce_v6_0_early_init()
2659 return -EINVAL; in dce_v6_0_early_init()
2673 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2674 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v6_0_sw_init()
2680 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v6_0_sw_init()
2685 /* HPD hotplug */ in dce_v6_0_sw_init()
2686 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); in dce_v6_0_sw_init()
2690 adev->mode_info.mode_config_initialized = true; in dce_v6_0_sw_init()
2692 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v6_0_sw_init()
2693 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v6_0_sw_init()
2694 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2695 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2696 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v6_0_sw_init()
2697 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v6_0_sw_init()
2698 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v6_0_sw_init()
2704 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2705 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2708 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2718 return -EINVAL; in dce_v6_0_sw_init()
2729 /* Disable vblank IRQs aggressively for power-saving */ in dce_v6_0_sw_init()
2731 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v6_0_sw_init()
2733 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v6_0_sw_init()
2737 /* Pre-DCE11 */ in dce_v6_0_sw_init()
2738 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v6_0_sw_init()
2750 drm_edid_free(adev->mode_info.bios_hardcoded_edid); in dce_v6_0_sw_fini()
2758 adev->mode_info.mode_config_initialized = false; in dce_v6_0_sw_fini()
2772 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v6_0_hw_init()
2774 /* initialize hpd */ in dce_v6_0_hw_init()
2777 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_init()
2778 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_init()
2793 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_fini()
2794 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_fini()
2799 flush_delayed_work(&adev->hotplug_work); in dce_v6_0_hw_fini()
2812 adev->mode_info.bl_level = in dce_v6_0_suspend()
2824 adev->mode_info.bl_level); in dce_v6_0_resume()
2829 if (adev->mode_info.bl_encoder) { in dce_v6_0_resume()
2831 adev->mode_info.bl_encoder); in dce_v6_0_resume()
2832 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v6_0_resume()
2853 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); in dce_v6_0_soft_reset()
2863 if (crtc >= adev->mode_info.num_crtc) { in dce_v6_0_set_crtc_vblank_interrupt_state()
2922 if (type >= adev->mode_info.num_hpd) { in dce_v6_0_set_hpd_interrupt_state()
2997 unsigned crtc = entry->src_id - 1; in dce_v6_0_crtc_irq()
3002 switch (entry->src_data[0]) { in dce_v6_0_crtc_irq()
3023 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_crtc_irq()
3037 if (type >= adev->mode_info.num_crtc) { in dce_v6_0_set_pageflip_interrupt_state()
3039 return -EINVAL; in dce_v6_0_set_pageflip_interrupt_state()
3062 crtc_id = (entry->src_id - 8) >> 1; in dce_v6_0_pageflip_irq()
3063 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3065 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v6_0_pageflip_irq()
3067 return -EINVAL; in dce_v6_0_pageflip_irq()
3079 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3080 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3081 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v6_0_pageflip_irq()
3082 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v6_0_pageflip_irq()
3084 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3086 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3091 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3092 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3095 if (works->event) in dce_v6_0_pageflip_irq()
3096 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3098 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3100 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()
3101 schedule_work(&works->unpin_work); in dce_v6_0_pageflip_irq()
3111 unsigned hpd; in dce_v6_0_hpd_irq() local
3113 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_irq()
3114 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_hpd_irq()
3118 hpd = entry->src_data[0]; in dce_v6_0_hpd_irq()
3119 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3120 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
3123 dce_v6_0_hpd_int_ack(adev, hpd); in dce_v6_0_hpd_irq()
3124 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v6_0_hpd_irq()
3125 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v6_0_hpd_irq()
3172 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v6_0_encoder_mode_set()
3178 dce_v6_0_set_interleave(encoder->crtc, mode); in dce_v6_0_encoder_mode_set()
3189 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_encoder_prepare()
3193 if ((amdgpu_encoder->active_device & in dce_v6_0_encoder_prepare()
3197 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_prepare()
3199 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); in dce_v6_0_encoder_prepare()
3200 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v6_0_encoder_prepare()
3201 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v6_0_encoder_prepare()
3211 if (amdgpu_connector->router.cd_valid) in dce_v6_0_encoder_prepare()
3215 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v6_0_encoder_prepare()
3229 struct drm_device *dev = encoder->dev; in dce_v6_0_encoder_commit()
3249 dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_disable()
3250 dig->dig_encoder = -1; in dce_v6_0_encoder_disable()
3252 amdgpu_encoder->active_device = 0; in dce_v6_0_encoder_disable()
3324 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_destroy()
3326 kfree(amdgpu_encoder->enc_priv); in dce_v6_0_encoder_destroy()
3345 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_encoder_add()
3347 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v6_0_encoder_add()
3348 amdgpu_encoder->devices |= supported_device; in dce_v6_0_encoder_add()
3359 encoder = &amdgpu_encoder->base; in dce_v6_0_encoder_add()
3360 switch (adev->mode_info.num_crtc) { in dce_v6_0_encoder_add()
3362 encoder->possible_crtcs = 0x1; in dce_v6_0_encoder_add()
3366 encoder->possible_crtcs = 0x3; in dce_v6_0_encoder_add()
3369 encoder->possible_crtcs = 0xf; in dce_v6_0_encoder_add()
3372 encoder->possible_crtcs = 0x3f; in dce_v6_0_encoder_add()
3376 amdgpu_encoder->enc_priv = NULL; in dce_v6_0_encoder_add()
3377 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v6_0_encoder_add()
3378 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v6_0_encoder_add()
3379 amdgpu_encoder->devices = supported_device; in dce_v6_0_encoder_add()
3380 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v6_0_encoder_add()
3381 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v6_0_encoder_add()
3382 amdgpu_encoder->is_ext_encoder = false; in dce_v6_0_encoder_add()
3383 amdgpu_encoder->caps = caps; in dce_v6_0_encoder_add()
3385 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_encoder_add()
3397 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v6_0_encoder_add()
3398 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v6_0_encoder_add()
3401 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3402 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v6_0_encoder_add()
3405 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3409 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3423 amdgpu_encoder->is_ext_encoder = true; in dce_v6_0_encoder_add()
3424 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_add()
3427 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v6_0_encoder_add()
3454 adev->mode_info.funcs = &dce_v6_0_display_funcs; in dce_v6_0_set_display_funcs()
3474 if (adev->mode_info.num_crtc > 0) in dce_v6_0_set_irq_funcs()
3475 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3477 adev->crtc_irq.num_types = 0; in dce_v6_0_set_irq_funcs()
3478 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; in dce_v6_0_set_irq_funcs()
3480 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3481 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; in dce_v6_0_set_irq_funcs()
3483 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v6_0_set_irq_funcs()
3484 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; in dce_v6_0_set_irq_funcs()