266 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_page_flip()
269 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_page_flip()
271 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
274 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
277 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
280 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v11_0_page_flip()
609 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_fmt()
660 	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);  in dce_v11_0_line_buffer_adjust()
662 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_line_buffer_adjust()
1157 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1159 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1160 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1163 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1166 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1167 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1170 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1172 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v11_0_program_watermarks()
1890 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v11_0_grph_enable()
1892 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_grph_enable()
2069 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_do_set_base()
2072 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_do_set_base()
2074 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2076 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2078 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2080 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2082 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v11_0_crtc_do_set_base()
2083 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v11_0_crtc_do_set_base()
2090 	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_do_set_base()
2095 	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_do_set_base()
2100 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2101 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2102 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2103 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2104 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v11_0_crtc_do_set_base()
2105 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v11_0_crtc_do_set_base()
2108 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v11_0_crtc_do_set_base()
2112 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2117 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2121 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2125 	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2150 	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);  in dce_v11_0_set_interleave()
2155 	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_set_interleave()
2169 	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2171 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2173 	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2175 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2177 	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2179 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2181 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2183 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2184 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2185 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2187 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2188 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2189 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2191 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2192 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v11_0_crtc_load_lut()
2194 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2199 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_load_lut()
2205 	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2209 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2211 	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2213 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2215 	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2217 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2219 	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2221 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2224 	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2228 	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2230 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2370 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v11_0_lock_cursor()
2375 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v11_0_lock_cursor()
2384 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_hide_cursor()
2386 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_hide_cursor()
2395 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_show_cursor()
2397 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_show_cursor()
2400 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_show_cursor()
2403 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_show_cursor()
2430 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v11_0_cursor_move_locked()
2431 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v11_0_cursor_move_locked()
2432 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v11_0_cursor_move_locked()
2826 		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2829 		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2832 		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2835 		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2838 		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2841 		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;  in dce_v11_0_crtc_init()