Lines Matching +full:hpd +full:- +full:pin
55 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
94 uint32_t hpd; member
100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
165 switch (adev->asic_type) { in dce_v11_0_init_golden_registers()
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
215 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
218 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
223 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in dce_v11_0_vblank_get_counter()
234 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_init()
235 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_init()
243 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_fini()
244 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_fini()
248 * dce_v11_0_page_flip - pageflip callback.
261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip()
262 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v11_0_page_flip()
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
272 fb->pitches[0] / fb->format->cpp[0]); in dce_v11_0_page_flip()
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
286 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v11_0_crtc_get_scanoutpos()
287 return -EINVAL; in dce_v11_0_crtc_get_scanoutpos()
296 * dce_v11_0_hpd_sense - hpd sense callback.
299 * @hpd: hpd (hotplug detect) pin
305 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_sense() argument
309 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_sense()
312 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v11_0_hpd_sense()
320 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
323 * @hpd: hpd (hotplug detect) pin
325 * Set the polarity of the hpd pin (evergreen+).
328 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_set_polarity() argument
331 bool connected = dce_v11_0_hpd_sense(adev, hpd); in dce_v11_0_hpd_set_polarity()
333 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_set_polarity()
336 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
345 * dce_v11_0_hpd_init - hpd setup callback.
349 * Setup the hpd pins used by the card (evergreen+).
350 * Enable the pin, set the polarity, and enable the hpd interrupts.
363 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_init()
366 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v11_0_hpd_init()
367 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v11_0_hpd_init()
368 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v11_0_hpd_init()
373 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
375 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
379 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
381 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
383 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
390 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
392 dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
393 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
394 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
400 * dce_v11_0_hpd_fini - hpd tear down callback.
404 * Tear down the hpd pins used by the card (evergreen+).
405 * Disable the hpd interrupts.
418 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_fini()
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_fini()
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_fini()
425 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_fini()
441 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
450 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
491 switch (adev->asic_type) { in dce_v11_0_get_num_crtc()
538 struct drm_device *dev = encoder->dev; in dce_v11_0_program_fmt()
541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_program_fmt()
550 dither = amdgpu_connector->dither; in dce_v11_0_program_fmt()
554 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v11_0_program_fmt()
558 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v11_0_program_fmt()
559 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v11_0_program_fmt()
609 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
615 * dce_v11_0_line_buffer_adjust - Set up the line buffer
631 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust()
640 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
641 if (mode->crtc_hdisplay < 1920) { in dce_v11_0_line_buffer_adjust()
644 } else if (mode->crtc_hdisplay < 2560) { in dce_v11_0_line_buffer_adjust()
647 } else if (mode->crtc_hdisplay < 4096) { in dce_v11_0_line_buffer_adjust()
649 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
653 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
660 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
662 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
668 for (i = 0; i < adev->usec_timeout; i++) { in dce_v11_0_line_buffer_adjust()
675 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
692 * cik_get_number_of_dram_channels - get the number of dram channels
729 u32 yclk; /* bandwidth per dram data pin in kHz */
744 * dce_v11_0_dram_bandwidth - get the dram bandwidth
760 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()
762 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()
773 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
789 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()
791 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()
802 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
818 sclk.full = dfixed_const(wm->sclk); in dce_v11_0_data_return_bandwidth()
831 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
847 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v11_0_dmif_request_bandwidth()
862 * dce_v11_0_available_bandwidth - get the min available bandwidth
881 * dce_v11_0_average_bandwidth - get the average available bandwidth
902 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v11_0_average_bandwidth()
904 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v11_0_average_bandwidth()
905 src_width.full = dfixed_const(wm->src_width); in dce_v11_0_average_bandwidth()
907 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()
914 * dce_v11_0_latency_watermark - get the latency watermark
929 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v11_0_latency_watermark()
930 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
931 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
937 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
942 if ((wm->vsc.full > a.full) || in dce_v11_0_latency_watermark()
943 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
944 (wm->vtaps >= 5) || in dce_v11_0_latency_watermark()
945 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v11_0_latency_watermark()
951 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
953 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v11_0_latency_watermark()
956 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v11_0_latency_watermark()
958 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v11_0_latency_watermark()
965 if (line_fill_time < wm->active_time) in dce_v11_0_latency_watermark()
968 return latency + (line_fill_time - wm->active_time); in dce_v11_0_latency_watermark()
973 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
986 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
993 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1006 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1013 * dce_v11_0_check_latency_hiding - check latency hiding
1023 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1024 u32 line_time = wm->active_time + wm->blank_time; in dce_v11_0_check_latency_hiding()
1030 if (wm->vsc.full > a.full) in dce_v11_0_check_latency_hiding()
1033 if (lb_partitions <= (wm->vtaps + 1)) in dce_v11_0_check_latency_hiding()
1039 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v11_0_check_latency_hiding()
1048 * dce_v11_0_program_watermarks - program display watermarks
1062 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v11_0_program_watermarks()
1069 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1070 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v11_0_program_watermarks()
1071 (u32)mode->clock); in dce_v11_0_program_watermarks()
1072 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v11_0_program_watermarks()
1073 (u32)mode->clock); in dce_v11_0_program_watermarks()
1077 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1083 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1084 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1087 wm_high.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1088 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1090 wm_high.blank_time = line_time - wm_high.active_time; in dce_v11_0_program_watermarks()
1092 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1094 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1096 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1111 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1116 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1122 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1123 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1126 wm_low.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1127 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1129 wm_low.blank_time = line_time - wm_low.active_time; in dce_v11_0_program_watermarks()
1131 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1133 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1135 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1150 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1153 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
1157 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1159 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1160 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1163 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1167 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1170 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1172 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
1175 amdgpu_crtc->line_time = line_time; in dce_v11_0_program_watermarks()
1176 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v11_0_program_watermarks()
1177 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v11_0_program_watermarks()
1179 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v11_0_program_watermarks()
1183 * dce_v11_0_bandwidth_update - program display watermarks
1198 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1199 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v11_0_bandwidth_update()
1202 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1203 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v11_0_bandwidth_update()
1204 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1205 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v11_0_bandwidth_update()
1215 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_connected_pins()
1216 offset = adev->mode_info.audio.pin[i].offset; in dce_v11_0_audio_get_connected_pins()
1222 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_get_connected_pins()
1224 adev->mode_info.audio.pin[i].connected = true; in dce_v11_0_audio_get_connected_pins()
1234 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_pin()
1235 if (adev->mode_info.audio.pin[i].connected) in dce_v11_0_audio_get_pin()
1236 return &adev->mode_info.audio.pin[i]; in dce_v11_0_audio_get_pin()
1244 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_afmt_audio_select_pin()
1246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_audio_select_pin()
1249 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_afmt_audio_select_pin()
1252 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1253 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1254 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1260 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_latency_fields()
1263 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_latency_fields()
1270 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_latency_fields()
1275 if (connector->encoder == encoder) { in dce_v11_0_audio_write_latency_fields()
1287 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_audio_write_latency_fields()
1289 if (connector->latency_present[interlace]) { in dce_v11_0_audio_write_latency_fields()
1291 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1293 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1300 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_latency_fields()
1306 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_speaker_allocation()
1309 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_speaker_allocation()
1317 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_speaker_allocation()
1322 if (connector->encoder == encoder) { in dce_v11_0_audio_write_speaker_allocation()
1334 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); in dce_v11_0_audio_write_speaker_allocation()
1341 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1354 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1362 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_sad_regs()
1365 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_sad_regs()
1387 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_sad_regs()
1392 if (connector->encoder == encoder) { in dce_v11_0_audio_write_sad_regs()
1404 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); in dce_v11_0_audio_write_sad_regs()
1414 int max_channels = -1; in dce_v11_0_audio_write_sad_regs()
1420 if (sad->format == eld_reg_to_type[i][1]) { in dce_v11_0_audio_write_sad_regs()
1421 if (sad->channels > max_channels) { in dce_v11_0_audio_write_sad_regs()
1423 MAX_CHANNELS, sad->channels); in dce_v11_0_audio_write_sad_regs()
1425 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v11_0_audio_write_sad_regs()
1427 SUPPORTED_FREQUENCIES, sad->freq); in dce_v11_0_audio_write_sad_regs()
1428 max_channels = sad->channels; in dce_v11_0_audio_write_sad_regs()
1431 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v11_0_audio_write_sad_regs()
1432 stereo_freqs |= sad->freq; in dce_v11_0_audio_write_sad_regs()
1440 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1447 struct amdgpu_audio_pin *pin, in dce_v11_0_audio_enable() argument
1450 if (!pin) in dce_v11_0_audio_enable()
1453 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v11_0_audio_enable()
1476 adev->mode_info.audio.enabled = true; in dce_v11_0_audio_init()
1478 switch (adev->asic_type) { in dce_v11_0_audio_init()
1481 adev->mode_info.audio.num_pins = 7; in dce_v11_0_audio_init()
1485 adev->mode_info.audio.num_pins = 8; in dce_v11_0_audio_init()
1489 adev->mode_info.audio.num_pins = 6; in dce_v11_0_audio_init()
1492 return -EINVAL; in dce_v11_0_audio_init()
1495 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_init()
1496 adev->mode_info.audio.pin[i].channels = -1; in dce_v11_0_audio_init()
1497 adev->mode_info.audio.pin[i].rate = -1; in dce_v11_0_audio_init()
1498 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v11_0_audio_init()
1499 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v11_0_audio_init()
1500 adev->mode_info.audio.pin[i].category_code = 0; in dce_v11_0_audio_init()
1501 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_init()
1502 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v11_0_audio_init()
1503 adev->mode_info.audio.pin[i].id = i; in dce_v11_0_audio_init()
1506 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_init()
1519 if (!adev->mode_info.audio.enabled) in dce_v11_0_audio_fini()
1522 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v11_0_audio_fini()
1523 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_fini()
1525 adev->mode_info.audio.enabled = false; in dce_v11_0_audio_fini()
1533 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_ACR()
1537 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_ACR()
1540 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1542 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1543 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1545 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1547 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1549 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1550 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1552 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1554 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1556 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1557 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1559 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1569 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_avi_infoframe()
1572 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_avi_infoframe()
1576 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1578 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1580 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1582 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1588 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_set_dto()
1591 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_set_dto()
1592 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_audio_set_dto()
1597 if (!dig || !dig->afmt) in dce_v11_0_audio_set_dto()
1607 amdgpu_crtc->crtc_id); in dce_v11_0_audio_set_dto()
1619 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_setmode()
1622 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_setmode()
1630 if (!dig || !dig->afmt) in dce_v11_0_afmt_setmode()
1634 if (!dig->afmt->enabled) in dce_v11_0_afmt_setmode()
1638 if (encoder->crtc) { in dce_v11_0_afmt_setmode()
1639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_afmt_setmode()
1640 bpc = amdgpu_crtc->bpc; in dce_v11_0_afmt_setmode()
1644 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); in dce_v11_0_afmt_setmode()
1645 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_setmode()
1647 dce_v11_0_audio_set_dto(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1649 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1651 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1653 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v11_0_afmt_setmode()
1655 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1665 connector->name, bpc); in dce_v11_0_afmt_setmode()
1671 connector->name); in dce_v11_0_afmt_setmode()
1677 connector->name); in dce_v11_0_afmt_setmode()
1680 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1682 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1686 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1688 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1693 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1695 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1698 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1700 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1703 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1705 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v11_0_afmt_setmode()
1707 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1712 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1714 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1717 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1719 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1728 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1730 dce_v11_0_afmt_update_ACR(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1732 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1734 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1736 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1738 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1740 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1747 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1751 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v11_0_afmt_setmode()
1772 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1777 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1779 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1781 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1783 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1786 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1788 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v11_0_afmt_setmode()
1789 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v11_0_afmt_setmode()
1790 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1791 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1794 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); in dce_v11_0_afmt_setmode()
1799 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_enable()
1802 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_enable()
1804 if (!dig || !dig->afmt) in dce_v11_0_afmt_enable()
1808 if (enable && dig->afmt->enabled) in dce_v11_0_afmt_enable()
1810 if (!enable && !dig->afmt->enabled) in dce_v11_0_afmt_enable()
1813 if (!enable && dig->afmt->pin) { in dce_v11_0_afmt_enable()
1814 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_enable()
1815 dig->afmt->pin = NULL; in dce_v11_0_afmt_enable()
1818 dig->afmt->enabled = enable; in dce_v11_0_afmt_enable()
1821 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v11_0_afmt_enable()
1828 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v11_0_afmt_init()
1829 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_init()
1832 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_init()
1833 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v11_0_afmt_init()
1834 if (adev->mode_info.afmt[i]) { in dce_v11_0_afmt_init()
1835 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v11_0_afmt_init()
1836 adev->mode_info.afmt[i]->id = i; in dce_v11_0_afmt_init()
1840 kfree(adev->mode_info.afmt[j]); in dce_v11_0_afmt_init()
1841 adev->mode_info.afmt[j] = NULL; in dce_v11_0_afmt_init()
1843 return -ENOMEM; in dce_v11_0_afmt_init()
1853 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_fini()
1854 kfree(adev->mode_info.afmt[i]); in dce_v11_0_afmt_fini()
1855 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_fini()
1872 struct drm_device *dev = crtc->dev; in dce_v11_0_vga_enable()
1876 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v11_0_vga_enable()
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v11_0_vga_enable()
1880 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v11_0_vga_enable()
1886 struct drm_device *dev = crtc->dev; in dce_v11_0_grph_enable()
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable()
1892 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable()
1900 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_do_set_base()
1914 if (!atomic && !crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
1922 target_fb = crtc->primary->fb; in dce_v11_0_crtc_do_set_base()
1927 obj = target_fb->obj[0]; in dce_v11_0_crtc_do_set_base()
1934 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v11_0_crtc_do_set_base()
1938 return -EINVAL; in dce_v11_0_crtc_do_set_base()
1948 switch (target_fb->format->format) { in dce_v11_0_crtc_do_set_base()
2005 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2016 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2032 &target_fb->format->format); in dce_v11_0_crtc_do_set_base()
2033 return -EINVAL; in dce_v11_0_crtc_do_set_base()
2069 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2072 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2074 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2076 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2078 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2080 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2082 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()
2083 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
2090 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2095 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2100 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2101 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2102 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2103 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2104 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v11_0_crtc_do_set_base()
2105 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v11_0_crtc_do_set_base()
2107 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v11_0_crtc_do_set_base()
2108 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v11_0_crtc_do_set_base()
2112 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2113 target_fb->height); in dce_v11_0_crtc_do_set_base()
2117 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2119 viewport_w = crtc->mode.hdisplay; in dce_v11_0_crtc_do_set_base()
2120 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v11_0_crtc_do_set_base()
2121 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2125 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2127 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
2128 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v11_0_crtc_do_set_base()
2145 struct drm_device *dev = crtc->dev; in dce_v11_0_set_interleave()
2150 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2151 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_set_interleave()
2155 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2161 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_load_lut()
2167 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v11_0_crtc_load_lut()
2169 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2171 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2173 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2175 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2177 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2179 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2181 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2183 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2184 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2185 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2187 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2188 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2189 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2191 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2192 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v11_0_crtc_load_lut()
2194 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2195 r = crtc->gamma_store; in dce_v11_0_crtc_load_lut()
2196 g = r + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2197 b = g + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2199 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_load_lut()
2205 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2209 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2211 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2213 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2215 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2217 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2219 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2221 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2224 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2228 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2230 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2236 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_dig_encoder()
2238 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_dig_encoder()
2240 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2245 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2250 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2257 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_dig_encoder()
2263 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2268 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2279 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2281 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2287 struct drm_device *dev = crtc->dev; in dce_v11_0_pick_pll()
2292 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_pick_pll()
2293 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_pick_pll()
2294 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_pick_pll()
2295 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_pick_pll()
2297 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_pick_pll()
2298 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_pll()
2300 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_pick_pll()
2303 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_pll()
2305 if (dig->linkb) in dce_v11_0_pick_pll()
2310 if (dig->linkb) in dce_v11_0_pick_pll()
2315 if (dig->linkb) in dce_v11_0_pick_pll()
2320 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_pll()
2325 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v11_0_pick_pll()
2326 if (adev->clock.dp_extclk) in dce_v11_0_pick_pll()
2344 if (adev->flags & AMD_IS_APU) { in dce_v11_0_pick_pll()
2366 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_lock_cursor()
2370 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
2375 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v11_0_lock_cursor()
2381 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_hide_cursor()
2384 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2386 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2392 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_show_cursor()
2395 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2396 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2397 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2398 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2400 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2403 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
2410 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_cursor_move_locked()
2413 amdgpu_crtc->cursor_x = x; in dce_v11_0_cursor_move_locked()
2414 amdgpu_crtc->cursor_y = y; in dce_v11_0_cursor_move_locked()
2417 x += crtc->x; in dce_v11_0_cursor_move_locked()
2418 y += crtc->y; in dce_v11_0_cursor_move_locked()
2419 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v11_0_cursor_move_locked()
2422 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v11_0_cursor_move_locked()
2426 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v11_0_cursor_move_locked()
2430 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v11_0_cursor_move_locked()
2431 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v11_0_cursor_move_locked()
2432 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked()
2433 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v11_0_cursor_move_locked()
2470 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v11_0_crtc_cursor_set2()
2471 (height > amdgpu_crtc->max_cursor_height)) { in dce_v11_0_crtc_cursor_set2()
2473 return -EINVAL; in dce_v11_0_crtc_cursor_set2()
2478 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v11_0_crtc_cursor_set2()
2479 return -ENOENT; in dce_v11_0_crtc_cursor_set2()
2489 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v11_0_crtc_cursor_set2()
2493 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); in dce_v11_0_crtc_cursor_set2()
2497 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v11_0_crtc_cursor_set2()
2501 if (width != amdgpu_crtc->cursor_width || in dce_v11_0_crtc_cursor_set2()
2502 height != amdgpu_crtc->cursor_height || in dce_v11_0_crtc_cursor_set2()
2503 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v11_0_crtc_cursor_set2()
2504 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v11_0_crtc_cursor_set2()
2507 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v11_0_crtc_cursor_set2()
2508 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v11_0_crtc_cursor_set2()
2512 amdgpu_crtc->cursor_width = width; in dce_v11_0_crtc_cursor_set2()
2513 amdgpu_crtc->cursor_height = height; in dce_v11_0_crtc_cursor_set2()
2514 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v11_0_crtc_cursor_set2()
2515 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v11_0_crtc_cursor_set2()
2522 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_crtc_cursor_set2()
2523 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2529 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2532 amdgpu_crtc->cursor_bo = obj; in dce_v11_0_crtc_cursor_set2()
2540 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_cursor_reset()
2543 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v11_0_cursor_reset()
2544 amdgpu_crtc->cursor_y); in dce_v11_0_cursor_reset()
2584 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_dpms()
2591 amdgpu_crtc->enabled = true; in dce_v11_0_crtc_dpms()
2598 amdgpu_crtc->crtc_id); in dce_v11_0_crtc_dpms()
2599 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v11_0_crtc_dpms()
2600 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v11_0_crtc_dpms()
2608 if (amdgpu_crtc->enabled) { in dce_v11_0_crtc_dpms()
2614 amdgpu_crtc->enabled = false; in dce_v11_0_crtc_dpms()
2638 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_disable()
2644 if (crtc->primary->fb) { in dce_v11_0_crtc_disable()
2648 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v11_0_crtc_disable()
2662 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_crtc_disable()
2663 if (adev->mode_info.crtcs[i] && in dce_v11_0_crtc_disable()
2664 adev->mode_info.crtcs[i]->enabled && in dce_v11_0_crtc_disable()
2665 i != amdgpu_crtc->crtc_id && in dce_v11_0_crtc_disable()
2666 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable()
2674 switch (amdgpu_crtc->pll_id) { in dce_v11_0_crtc_disable()
2679 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2689 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2696 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_disable()
2697 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_disable()
2698 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_disable()
2699 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_disable()
2708 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_set()
2711 if (!amdgpu_crtc->adjusted_clock) in dce_v11_0_crtc_mode_set()
2712 return -EINVAL; in dce_v11_0_crtc_mode_set()
2714 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_crtc_mode_set()
2715 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_crtc_mode_set()
2716 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_crtc_mode_set()
2717 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_crtc_mode_set()
2719 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2721 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2724 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, in dce_v11_0_crtc_mode_set()
2725 amdgpu_crtc->pll_id, in dce_v11_0_crtc_mode_set()
2726 encoder_mode, amdgpu_encoder->encoder_id, in dce_v11_0_crtc_mode_set()
2727 adjusted_mode->clock, 0, 0, 0, 0, in dce_v11_0_crtc_mode_set()
2728 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in dce_v11_0_crtc_mode_set()
2738 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v11_0_crtc_mode_set()
2748 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_fixup()
2752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_crtc_mode_fixup()
2753 if (encoder->crtc == crtc) { in dce_v11_0_crtc_mode_fixup()
2754 amdgpu_crtc->encoder = encoder; in dce_v11_0_crtc_mode_fixup()
2755 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v11_0_crtc_mode_fixup()
2759 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v11_0_crtc_mode_fixup()
2760 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_mode_fixup()
2761 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_mode_fixup()
2769 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); in dce_v11_0_crtc_mode_fixup()
2770 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v11_0_crtc_mode_fixup()
2771 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v11_0_crtc_mode_fixup()
2772 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_crtc_mode_fixup()
2810 return -ENOMEM; in dce_v11_0_crtc_init()
2812 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); in dce_v11_0_crtc_init()
2814 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v11_0_crtc_init()
2815 amdgpu_crtc->crtc_id = index; in dce_v11_0_crtc_init()
2816 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init()
2818 amdgpu_crtc->max_cursor_width = 128; in dce_v11_0_crtc_init()
2819 amdgpu_crtc->max_cursor_height = 128; in dce_v11_0_crtc_init()
2820 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v11_0_crtc_init()
2821 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v11_0_crtc_init()
2823 switch (amdgpu_crtc->crtc_id) { in dce_v11_0_crtc_init()
2826 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2829 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2832 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2835 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2838 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2841 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_init()
2846 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_init()
2847 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_init()
2848 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_init()
2849 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); in dce_v11_0_crtc_init()
2858 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; in dce_v11_0_early_init()
2859 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; in dce_v11_0_early_init()
2863 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); in dce_v11_0_early_init()
2865 switch (adev->asic_type) { in dce_v11_0_early_init()
2867 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2868 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2871 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2872 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2876 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2877 adev->mode_info.num_dig = 6; in dce_v11_0_early_init()
2881 adev->mode_info.num_hpd = 5; in dce_v11_0_early_init()
2882 adev->mode_info.num_dig = 5; in dce_v11_0_early_init()
2886 return -EINVAL; in dce_v11_0_early_init()
2899 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2900 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v11_0_sw_init()
2906 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v11_0_sw_init()
2911 /* HPD hotplug */ in dce_v11_0_sw_init()
2912 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v11_0_sw_init()
2916 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v11_0_sw_init()
2918 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v11_0_sw_init()
2920 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2921 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2923 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v11_0_sw_init()
2924 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v11_0_sw_init()
2926 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v11_0_sw_init()
2932 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2933 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2937 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2946 return -EINVAL; in dce_v11_0_sw_init()
2957 /* Disable vblank IRQs aggressively for power-saving */ in dce_v11_0_sw_init()
2959 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v11_0_sw_init()
2961 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v11_0_sw_init()
2965 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v11_0_sw_init()
2970 adev->mode_info.mode_config_initialized = true; in dce_v11_0_sw_init()
2978 drm_edid_free(adev->mode_info.bios_hardcoded_edid); in dce_v11_0_sw_fini()
2987 adev->mode_info.mode_config_initialized = false; in dce_v11_0_sw_fini()
3004 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_hw_init()
3005 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_hw_init()
3006 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_hw_init()
3007 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_hw_init()
3008 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, in dce_v11_0_hw_init()
3013 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v11_0_hw_init()
3016 /* initialize hpd */ in dce_v11_0_hw_init()
3019 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_init()
3020 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_init()
3035 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_fini()
3036 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_fini()
3041 flush_delayed_work(&adev->hotplug_work); in dce_v11_0_hw_fini()
3055 adev->mode_info.bl_level = in dce_v11_0_suspend()
3067 adev->mode_info.bl_level); in dce_v11_0_resume()
3072 if (adev->mode_info.bl_encoder) { in dce_v11_0_resume()
3074 adev->mode_info.bl_encoder); in dce_v11_0_resume()
3075 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v11_0_resume()
3105 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v11_0_soft_reset()
3127 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vblank_interrupt_state()
3156 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vline_interrupt_state()
3181 unsigned hpd, in dce_v11_0_set_hpd_irq_state() argument
3186 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_set_hpd_irq_state()
3187 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_set_hpd_irq_state()
3193 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3195 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3198 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3200 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3264 if (type >= adev->mode_info.num_crtc) { in dce_v11_0_set_pageflip_irq_state()
3266 return -EINVAL; in dce_v11_0_set_pageflip_irq_state()
3289 crtc_id = (entry->src_id - 8) >> 1; in dce_v11_0_pageflip_irq()
3290 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
3292 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v11_0_pageflip_irq()
3294 return -EINVAL; in dce_v11_0_pageflip_irq()
3306 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3307 works = amdgpu_crtc->pflip_works; in dce_v11_0_pageflip_irq()
3308 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v11_0_pageflip_irq()
3309 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v11_0_pageflip_irq()
3311 amdgpu_crtc->pflip_status, in dce_v11_0_pageflip_irq()
3313 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3318 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v11_0_pageflip_irq()
3319 amdgpu_crtc->pflip_works = NULL; in dce_v11_0_pageflip_irq()
3322 if(works->event) in dce_v11_0_pageflip_irq()
3323 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v11_0_pageflip_irq()
3325 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3327 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v11_0_pageflip_irq()
3328 schedule_work(&works->unpin_work); in dce_v11_0_pageflip_irq()
3334 int hpd) in dce_v11_0_hpd_int_ack() argument
3338 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_int_ack()
3339 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_hpd_int_ack()
3343 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3345 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
3353 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vblank_int_ack()
3368 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vline_int_ack()
3382 unsigned crtc = entry->src_id - 1; in dce_v11_0_crtc_irq()
3387 switch (entry->src_data[0]) { in dce_v11_0_crtc_irq()
3410 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_crtc_irq()
3422 unsigned hpd; in dce_v11_0_hpd_irq() local
3424 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_irq()
3425 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_hpd_irq()
3429 hpd = entry->src_data[0]; in dce_v11_0_hpd_irq()
3430 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3431 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
3434 dce_v11_0_hpd_int_ack(adev, hpd); in dce_v11_0_hpd_irq()
3435 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v11_0_hpd_irq()
3436 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v11_0_hpd_irq()
3480 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v11_0_encoder_mode_set()
3486 dce_v11_0_set_interleave(encoder->crtc, mode); in dce_v11_0_encoder_mode_set()
3496 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_encoder_prepare()
3500 if ((amdgpu_encoder->active_device & in dce_v11_0_encoder_prepare()
3504 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_prepare()
3506 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); in dce_v11_0_encoder_prepare()
3507 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v11_0_encoder_prepare()
3508 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v11_0_encoder_prepare()
3518 if (amdgpu_connector->router.cd_valid) in dce_v11_0_encoder_prepare()
3522 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v11_0_encoder_prepare()
3535 struct drm_device *dev = encoder->dev; in dce_v11_0_encoder_commit()
3553 dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_disable()
3554 dig->dig_encoder = -1; in dce_v11_0_encoder_disable()
3556 amdgpu_encoder->active_device = 0; in dce_v11_0_encoder_disable()
3620 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_destroy()
3622 kfree(amdgpu_encoder->enc_priv); in dce_v11_0_encoder_destroy()
3641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_encoder_add()
3643 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v11_0_encoder_add()
3644 amdgpu_encoder->devices |= supported_device; in dce_v11_0_encoder_add()
3655 encoder = &amdgpu_encoder->base; in dce_v11_0_encoder_add()
3656 switch (adev->mode_info.num_crtc) { in dce_v11_0_encoder_add()
3658 encoder->possible_crtcs = 0x1; in dce_v11_0_encoder_add()
3662 encoder->possible_crtcs = 0x3; in dce_v11_0_encoder_add()
3665 encoder->possible_crtcs = 0x7; in dce_v11_0_encoder_add()
3668 encoder->possible_crtcs = 0xf; in dce_v11_0_encoder_add()
3671 encoder->possible_crtcs = 0x1f; in dce_v11_0_encoder_add()
3674 encoder->possible_crtcs = 0x3f; in dce_v11_0_encoder_add()
3678 amdgpu_encoder->enc_priv = NULL; in dce_v11_0_encoder_add()
3680 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v11_0_encoder_add()
3681 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v11_0_encoder_add()
3682 amdgpu_encoder->devices = supported_device; in dce_v11_0_encoder_add()
3683 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v11_0_encoder_add()
3684 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v11_0_encoder_add()
3685 amdgpu_encoder->is_ext_encoder = false; in dce_v11_0_encoder_add()
3686 amdgpu_encoder->caps = caps; in dce_v11_0_encoder_add()
3688 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_encoder_add()
3700 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v11_0_encoder_add()
3701 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v11_0_encoder_add()
3704 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3705 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v11_0_encoder_add()
3708 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3712 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3726 amdgpu_encoder->is_ext_encoder = true; in dce_v11_0_encoder_add()
3727 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_add()
3730 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v11_0_encoder_add()
3757 adev->mode_info.funcs = &dce_v11_0_display_funcs; in dce_v11_0_set_display_funcs()
3777 if (adev->mode_info.num_crtc > 0) in dce_v11_0_set_irq_funcs()
3778 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3780 adev->crtc_irq.num_types = 0; in dce_v11_0_set_irq_funcs()
3781 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; in dce_v11_0_set_irq_funcs()
3783 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3784 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; in dce_v11_0_set_irq_funcs()
3786 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v11_0_set_irq_funcs()
3787 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; in dce_v11_0_set_irq_funcs()