Lines Matching +full:hpd +full:- +full:pin
55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
150 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
181 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
199 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
210 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_init()
211 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_init()
219 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_fini()
220 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_fini()
224 * dce_v10_0_page_flip - pageflip callback.
237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v10_0_page_flip()
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
248 fb->pitches[0] / fb->format->cpp[0]); in dce_v10_0_page_flip()
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
263 return -EINVAL; in dce_v10_0_crtc_get_scanoutpos()
272 * dce_v10_0_hpd_sense - hpd sense callback.
275 * @hpd: hpd (hotplug detect) pin
281 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
285 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
296 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
299 * @hpd: hpd (hotplug detect) pin
301 * Set the polarity of the hpd pin (evergreen+).
304 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
307 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
309 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
321 * dce_v10_0_hpd_init - hpd setup callback.
325 * Setup the hpd pins used by the card (evergreen+).
326 * Enable the pin, set the polarity, and enable the hpd interrupts.
339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v10_0_hpd_init()
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v10_0_hpd_init()
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v10_0_hpd_init()
349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
370 amdgpu_irq_get(adev, &adev->hpd_irq, in dce_v10_0_hpd_init()
371 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
377 * dce_v10_0_hpd_fini - hpd tear down callback.
381 * Tear down the hpd pins used by the card (evergreen+).
382 * Disable the hpd interrupts.
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
402 amdgpu_irq_put(adev, &adev->hpd_irq, in dce_v10_0_hpd_fini()
403 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
419 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
428 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
469 switch (adev->asic_type) { in dce_v10_0_get_num_crtc()
506 struct drm_device *dev = encoder->dev; in dce_v10_0_program_fmt()
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt()
518 dither = amdgpu_connector->dither; in dce_v10_0_program_fmt()
522 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v10_0_program_fmt()
526 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v10_0_program_fmt()
527 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v10_0_program_fmt()
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
583 * dce_v10_0_line_buffer_adjust - Set up the line buffer
599 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust()
608 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
609 if (mode->crtc_hdisplay < 1920) { in dce_v10_0_line_buffer_adjust()
612 } else if (mode->crtc_hdisplay < 2560) { in dce_v10_0_line_buffer_adjust()
615 } else if (mode->crtc_hdisplay < 4096) { in dce_v10_0_line_buffer_adjust()
617 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
621 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
636 for (i = 0; i < adev->usec_timeout; i++) { in dce_v10_0_line_buffer_adjust()
643 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
660 * cik_get_number_of_dram_channels - get the number of dram channels
697 u32 yclk; /* bandwidth per dram data pin in kHz */
712 * dce_v10_0_dram_bandwidth - get the dram bandwidth
728 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()
730 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()
741 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
757 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()
759 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()
770 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
786 sclk.full = dfixed_const(wm->sclk); in dce_v10_0_data_return_bandwidth()
799 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
815 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v10_0_dmif_request_bandwidth()
830 * dce_v10_0_available_bandwidth - get the min available bandwidth
849 * dce_v10_0_average_bandwidth - get the average available bandwidth
870 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v10_0_average_bandwidth()
872 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v10_0_average_bandwidth()
873 src_width.full = dfixed_const(wm->src_width); in dce_v10_0_average_bandwidth()
875 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
882 * dce_v10_0_latency_watermark - get the latency watermark
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v10_0_latency_watermark()
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
899 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
905 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
910 if ((wm->vsc.full > a.full) || in dce_v10_0_latency_watermark()
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
912 (wm->vtaps >= 5) || in dce_v10_0_latency_watermark()
913 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v10_0_latency_watermark()
919 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v10_0_latency_watermark()
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v10_0_latency_watermark()
926 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v10_0_latency_watermark()
933 if (line_fill_time < wm->active_time) in dce_v10_0_latency_watermark()
936 return latency + (line_fill_time - wm->active_time); in dce_v10_0_latency_watermark()
941 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
961 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
981 * dce_v10_0_check_latency_hiding - check latency hiding
991 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
992 u32 line_time = wm->active_time + wm->blank_time; in dce_v10_0_check_latency_hiding()
998 if (wm->vsc.full > a.full) in dce_v10_0_check_latency_hiding()
1001 if (lb_partitions <= (wm->vtaps + 1)) in dce_v10_0_check_latency_hiding()
1007 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v10_0_check_latency_hiding()
1016 * dce_v10_0_program_watermarks - program display watermarks
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v10_0_program_watermarks()
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1038 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v10_0_program_watermarks()
1039 (u32)mode->clock); in dce_v10_0_program_watermarks()
1040 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v10_0_program_watermarks()
1041 (u32)mode->clock); in dce_v10_0_program_watermarks()
1045 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1051 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1052 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1055 wm_high.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1056 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1058 wm_high.blank_time = line_time - wm_high.active_time; in dce_v10_0_program_watermarks()
1060 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1062 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1064 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1079 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1084 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1090 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1091 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1094 wm_low.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1095 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1097 wm_low.blank_time = line_time - wm_low.active_time; in dce_v10_0_program_watermarks()
1099 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1101 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1103 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1118 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
1143 amdgpu_crtc->line_time = line_time; in dce_v10_0_program_watermarks()
1144 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v10_0_program_watermarks()
1145 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v10_0_program_watermarks()
1147 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v10_0_program_watermarks()
1151 * dce_v10_0_bandwidth_update - program display watermarks
1166 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1167 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1170 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1171 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1173 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
1183 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_connected_pins()
1184 offset = adev->mode_info.audio.pin[i].offset; in dce_v10_0_audio_get_connected_pins()
1190 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_get_connected_pins()
1192 adev->mode_info.audio.pin[i].connected = true; in dce_v10_0_audio_get_connected_pins()
1202 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_pin()
1203 if (adev->mode_info.audio.pin[i].connected) in dce_v10_0_audio_get_pin()
1204 return &adev->mode_info.audio.pin[i]; in dce_v10_0_audio_get_pin()
1212 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_afmt_audio_select_pin()
1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_audio_select_pin()
1217 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1220 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1221 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1222 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1228 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_latency_fields()
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_latency_fields()
1238 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1243 if (connector->encoder == encoder) { in dce_v10_0_audio_write_latency_fields()
1255 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_audio_write_latency_fields()
1257 if (connector->latency_present[interlace]) { in dce_v10_0_audio_write_latency_fields()
1259 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1261 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1268 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1274 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_speaker_allocation()
1277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_speaker_allocation()
1285 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1290 if (connector->encoder == encoder) { in dce_v10_0_audio_write_speaker_allocation()
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); in dce_v10_0_audio_write_speaker_allocation()
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1330 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_sad_regs()
1333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_sad_regs()
1355 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1360 if (connector->encoder == encoder) { in dce_v10_0_audio_write_sad_regs()
1372 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); in dce_v10_0_audio_write_sad_regs()
1382 int max_channels = -1; in dce_v10_0_audio_write_sad_regs()
1388 if (sad->format == eld_reg_to_type[i][1]) { in dce_v10_0_audio_write_sad_regs()
1389 if (sad->channels > max_channels) { in dce_v10_0_audio_write_sad_regs()
1391 MAX_CHANNELS, sad->channels); in dce_v10_0_audio_write_sad_regs()
1393 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v10_0_audio_write_sad_regs()
1395 SUPPORTED_FREQUENCIES, sad->freq); in dce_v10_0_audio_write_sad_regs()
1396 max_channels = sad->channels; in dce_v10_0_audio_write_sad_regs()
1399 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v10_0_audio_write_sad_regs()
1400 stereo_freqs |= sad->freq; in dce_v10_0_audio_write_sad_regs()
1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1415 struct amdgpu_audio_pin *pin, in dce_v10_0_audio_enable() argument
1418 if (!pin) in dce_v10_0_audio_enable()
1421 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v10_0_audio_enable()
1442 adev->mode_info.audio.enabled = true; in dce_v10_0_audio_init()
1444 adev->mode_info.audio.num_pins = 7; in dce_v10_0_audio_init()
1446 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_init()
1447 adev->mode_info.audio.pin[i].channels = -1; in dce_v10_0_audio_init()
1448 adev->mode_info.audio.pin[i].rate = -1; in dce_v10_0_audio_init()
1449 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v10_0_audio_init()
1450 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v10_0_audio_init()
1451 adev->mode_info.audio.pin[i].category_code = 0; in dce_v10_0_audio_init()
1452 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_init()
1453 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v10_0_audio_init()
1454 adev->mode_info.audio.pin[i].id = i; in dce_v10_0_audio_init()
1457 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_init()
1470 if (!adev->mode_info.audio.enabled) in dce_v10_0_audio_fini()
1473 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v10_0_audio_fini()
1474 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_fini()
1476 adev->mode_info.audio.enabled = false; in dce_v10_0_audio_fini()
1484 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_ACR()
1488 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_ACR()
1491 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1493 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1494 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1496 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1498 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1500 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1501 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1503 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1505 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1507 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1508 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1510 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1520 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_avi_infoframe()
1523 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_avi_infoframe()
1527 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1529 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1531 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1533 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1539 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_set_dto()
1542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_set_dto()
1543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto()
1548 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1558 amdgpu_crtc->crtc_id); in dce_v10_0_audio_set_dto()
1570 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_setmode()
1573 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_setmode()
1581 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1585 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1589 if (encoder->crtc) { in dce_v10_0_afmt_setmode()
1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode()
1591 bpc = amdgpu_crtc->bpc; in dce_v10_0_afmt_setmode()
1595 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1596 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1598 dce_v10_0_audio_set_dto(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1600 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1602 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1604 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1606 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1616 connector->name, bpc); in dce_v10_0_afmt_setmode()
1622 connector->name); in dce_v10_0_afmt_setmode()
1628 connector->name); in dce_v10_0_afmt_setmode()
1631 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1633 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1637 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1639 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1644 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1646 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1649 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1654 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1656 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1658 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1663 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1665 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1668 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1670 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1679 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1681 dce_v10_0_afmt_update_ACR(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1683 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1685 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1687 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1689 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1691 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1698 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1702 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1723 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1728 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1730 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1732 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1734 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1737 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1739 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1740 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1741 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1742 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1745 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1750 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_enable()
1753 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_enable()
1755 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1759 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1761 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1764 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1765 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1766 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1769 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1772 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
1779 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v10_0_afmt_init()
1780 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_init()
1783 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_init()
1784 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v10_0_afmt_init()
1785 if (adev->mode_info.afmt[i]) { in dce_v10_0_afmt_init()
1786 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v10_0_afmt_init()
1787 adev->mode_info.afmt[i]->id = i; in dce_v10_0_afmt_init()
1791 kfree(adev->mode_info.afmt[j]); in dce_v10_0_afmt_init()
1792 adev->mode_info.afmt[j] = NULL; in dce_v10_0_afmt_init()
1794 return -ENOMEM; in dce_v10_0_afmt_init()
1804 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_fini()
1805 kfree(adev->mode_info.afmt[i]); in dce_v10_0_afmt_fini()
1806 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_fini()
1822 struct drm_device *dev = crtc->dev; in dce_v10_0_vga_enable()
1826 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v10_0_vga_enable()
1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v10_0_vga_enable()
1830 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v10_0_vga_enable()
1836 struct drm_device *dev = crtc->dev; in dce_v10_0_grph_enable()
1840 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v10_0_grph_enable()
1842 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_grph_enable()
1850 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_do_set_base()
1864 if (!atomic && !crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
1872 target_fb = crtc->primary->fb; in dce_v10_0_crtc_do_set_base()
1877 obj = target_fb->obj[0]; in dce_v10_0_crtc_do_set_base()
1884 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v10_0_crtc_do_set_base()
1888 return -EINVAL; in dce_v10_0_crtc_do_set_base()
1898 switch (target_fb->format->format) { in dce_v10_0_crtc_do_set_base()
1955 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1966 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1982 &target_fb->format->format); in dce_v10_0_crtc_do_set_base()
1983 return -EINVAL; in dce_v10_0_crtc_do_set_base()
2019 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2022 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2024 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2026 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2028 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2030 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2032 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2033 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v10_0_crtc_do_set_base()
2040 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2045 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2050 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2051 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2052 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2053 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2054 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v10_0_crtc_do_set_base()
2055 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v10_0_crtc_do_set_base()
2057 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v10_0_crtc_do_set_base()
2058 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v10_0_crtc_do_set_base()
2062 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2063 target_fb->height); in dce_v10_0_crtc_do_set_base()
2067 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2069 viewport_w = crtc->mode.hdisplay; in dce_v10_0_crtc_do_set_base()
2070 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v10_0_crtc_do_set_base()
2071 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2075 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2077 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2078 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v10_0_crtc_do_set_base()
2095 struct drm_device *dev = crtc->dev; in dce_v10_0_set_interleave()
2100 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2101 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_set_interleave()
2105 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2111 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_load_lut()
2117 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v10_0_crtc_load_lut()
2119 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2122 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2124 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2126 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2128 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2130 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2132 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2135 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2137 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2139 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2140 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2141 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2143 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2144 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2148 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v10_0_crtc_load_lut()
2150 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2151 r = crtc->gamma_store; in dce_v10_0_crtc_load_lut()
2152 g = r + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2153 b = g + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2155 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_load_lut()
2161 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2165 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2167 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2170 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2172 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2177 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2180 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2183 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2187 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2189 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2195 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_pick_dig_encoder()
2197 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_pick_dig_encoder()
2199 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2204 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2209 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2216 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v10_0_pick_dig_encoder()
2222 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2227 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2238 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2240 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2246 struct drm_device *dev = crtc->dev; in dce_v10_0_pick_pll()
2251 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v10_0_pick_pll()
2252 if (adev->clock.dp_extclk) in dce_v10_0_pick_pll()
2282 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_lock_cursor()
2286 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v10_0_lock_cursor()
2291 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v10_0_lock_cursor()
2297 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_hide_cursor()
2300 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2302 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2308 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_show_cursor()
2311 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2312 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2313 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2314 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2316 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2319 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
2326 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_cursor_move_locked()
2329 amdgpu_crtc->cursor_x = x; in dce_v10_0_cursor_move_locked()
2330 amdgpu_crtc->cursor_y = y; in dce_v10_0_cursor_move_locked()
2333 x += crtc->x; in dce_v10_0_cursor_move_locked()
2334 y += crtc->y; in dce_v10_0_cursor_move_locked()
2335 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v10_0_cursor_move_locked()
2338 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v10_0_cursor_move_locked()
2342 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v10_0_cursor_move_locked()
2346 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v10_0_cursor_move_locked()
2347 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v10_0_cursor_move_locked()
2348 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_cursor_move_locked()
2349 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v10_0_cursor_move_locked()
2386 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v10_0_crtc_cursor_set2()
2387 (height > amdgpu_crtc->max_cursor_height)) { in dce_v10_0_crtc_cursor_set2()
2389 return -EINVAL; in dce_v10_0_crtc_cursor_set2()
2394 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v10_0_crtc_cursor_set2()
2395 return -ENOENT; in dce_v10_0_crtc_cursor_set2()
2405 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v10_0_crtc_cursor_set2()
2409 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); in dce_v10_0_crtc_cursor_set2()
2413 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v10_0_crtc_cursor_set2()
2417 if (width != amdgpu_crtc->cursor_width || in dce_v10_0_crtc_cursor_set2()
2418 height != amdgpu_crtc->cursor_height || in dce_v10_0_crtc_cursor_set2()
2419 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v10_0_crtc_cursor_set2()
2420 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v10_0_crtc_cursor_set2()
2423 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v10_0_crtc_cursor_set2()
2424 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v10_0_crtc_cursor_set2()
2428 amdgpu_crtc->cursor_width = width; in dce_v10_0_crtc_cursor_set2()
2429 amdgpu_crtc->cursor_height = height; in dce_v10_0_crtc_cursor_set2()
2430 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v10_0_crtc_cursor_set2()
2431 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v10_0_crtc_cursor_set2()
2438 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_crtc_cursor_set2()
2439 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2445 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2448 amdgpu_crtc->cursor_bo = obj; in dce_v10_0_crtc_cursor_set2()
2456 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_cursor_reset()
2459 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2460 amdgpu_crtc->cursor_y); in dce_v10_0_cursor_reset()
2500 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_dpms()
2507 amdgpu_crtc->enabled = true; in dce_v10_0_crtc_dpms()
2514 amdgpu_crtc->crtc_id); in dce_v10_0_crtc_dpms()
2515 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v10_0_crtc_dpms()
2516 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v10_0_crtc_dpms()
2524 if (amdgpu_crtc->enabled) { in dce_v10_0_crtc_dpms()
2530 amdgpu_crtc->enabled = false; in dce_v10_0_crtc_dpms()
2554 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_disable()
2560 if (crtc->primary->fb) { in dce_v10_0_crtc_disable()
2564 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v10_0_crtc_disable()
2578 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_crtc_disable()
2579 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2580 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2581 i != amdgpu_crtc->crtc_id && in dce_v10_0_crtc_disable()
2582 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2590 switch (amdgpu_crtc->pll_id) { in dce_v10_0_crtc_disable()
2595 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2602 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_disable()
2603 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_disable()
2604 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_disable()
2605 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_disable()
2615 if (!amdgpu_crtc->adjusted_clock) in dce_v10_0_crtc_mode_set()
2616 return -EINVAL; in dce_v10_0_crtc_mode_set()
2625 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v10_0_crtc_mode_set()
2635 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_mode_fixup()
2639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_crtc_mode_fixup()
2640 if (encoder->crtc == crtc) { in dce_v10_0_crtc_mode_fixup()
2641 amdgpu_crtc->encoder = encoder; in dce_v10_0_crtc_mode_fixup()
2642 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v10_0_crtc_mode_fixup()
2646 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v10_0_crtc_mode_fixup()
2647 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_mode_fixup()
2648 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_mode_fixup()
2656 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2657 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
2658 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v10_0_crtc_mode_fixup()
2659 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v10_0_crtc_mode_fixup()
2697 return -ENOMEM; in dce_v10_0_crtc_init()
2699 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); in dce_v10_0_crtc_init()
2701 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v10_0_crtc_init()
2702 amdgpu_crtc->crtc_id = index; in dce_v10_0_crtc_init()
2703 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
2705 amdgpu_crtc->max_cursor_width = 128; in dce_v10_0_crtc_init()
2706 amdgpu_crtc->max_cursor_height = 128; in dce_v10_0_crtc_init()
2707 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v10_0_crtc_init()
2708 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v10_0_crtc_init()
2710 switch (amdgpu_crtc->crtc_id) { in dce_v10_0_crtc_init()
2713 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2716 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2719 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2722 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2725 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2728 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2732 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_init()
2733 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_init()
2734 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_init()
2735 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_init()
2736 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); in dce_v10_0_crtc_init()
2745 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; in dce_v10_0_early_init()
2746 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; in dce_v10_0_early_init()
2750 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); in dce_v10_0_early_init()
2752 switch (adev->asic_type) { in dce_v10_0_early_init()
2755 adev->mode_info.num_hpd = 6; in dce_v10_0_early_init()
2756 adev->mode_info.num_dig = 7; in dce_v10_0_early_init()
2760 return -EINVAL; in dce_v10_0_early_init()
2773 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2774 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v10_0_sw_init()
2780 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v10_0_sw_init()
2785 /* HPD hotplug */ in dce_v10_0_sw_init()
2786 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v10_0_sw_init()
2790 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v10_0_sw_init()
2792 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v10_0_sw_init()
2794 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2795 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2797 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v10_0_sw_init()
2798 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v10_0_sw_init()
2800 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v10_0_sw_init()
2806 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2807 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2810 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2819 return -EINVAL; in dce_v10_0_sw_init()
2830 /* Disable vblank IRQs aggressively for power-saving */ in dce_v10_0_sw_init()
2832 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v10_0_sw_init()
2834 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v10_0_sw_init()
2838 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v10_0_sw_init()
2843 adev->mode_info.mode_config_initialized = true; in dce_v10_0_sw_init()
2851 drm_edid_free(adev->mode_info.bios_hardcoded_edid); in dce_v10_0_sw_fini()
2860 adev->mode_info.mode_config_initialized = false; in dce_v10_0_sw_fini()
2876 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v10_0_hw_init()
2878 /* initialize hpd */ in dce_v10_0_hw_init()
2881 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_init()
2882 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_init()
2897 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_fini()
2898 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_fini()
2903 flush_delayed_work(&adev->hotplug_work); in dce_v10_0_hw_fini()
2917 adev->mode_info.bl_level = in dce_v10_0_suspend()
2929 adev->mode_info.bl_level); in dce_v10_0_resume()
2934 if (adev->mode_info.bl_encoder) { in dce_v10_0_resume()
2936 adev->mode_info.bl_encoder); in dce_v10_0_resume()
2937 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v10_0_resume()
2974 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
2996 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
3025 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3050 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3055 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3056 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3062 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3064 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3067 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3069 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3133 if (type >= adev->mode_info.num_crtc) { in dce_v10_0_set_pageflip_irq_state()
3135 return -EINVAL; in dce_v10_0_set_pageflip_irq_state()
3158 crtc_id = (entry->src_id - 8) >> 1; in dce_v10_0_pageflip_irq()
3159 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
3161 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v10_0_pageflip_irq()
3163 return -EINVAL; in dce_v10_0_pageflip_irq()
3175 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3176 works = amdgpu_crtc->pflip_works; in dce_v10_0_pageflip_irq()
3177 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dce_v10_0_pageflip_irq()
3178 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v10_0_pageflip_irq()
3180 amdgpu_crtc->pflip_status, in dce_v10_0_pageflip_irq()
3182 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3187 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v10_0_pageflip_irq()
3188 amdgpu_crtc->pflip_works = NULL; in dce_v10_0_pageflip_irq()
3191 if (works->event) in dce_v10_0_pageflip_irq()
3192 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v10_0_pageflip_irq()
3194 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3196 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v10_0_pageflip_irq()
3197 schedule_work(&works->unpin_work); in dce_v10_0_pageflip_irq()
3203 int hpd) in dce_v10_0_hpd_int_ack() argument
3207 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3208 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3212 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3214 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3222 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3237 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3251 unsigned crtc = entry->src_id - 1; in dce_v10_0_crtc_irq()
3255 switch (entry->src_data[0]) { in dce_v10_0_crtc_irq()
3278 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_crtc_irq()
3290 unsigned hpd; in dce_v10_0_hpd_irq() local
3292 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_irq()
3293 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_hpd_irq()
3297 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3298 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3299 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3302 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3303 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v10_0_hpd_irq()
3304 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()
3349 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v10_0_encoder_mode_set()
3355 dce_v10_0_set_interleave(encoder->crtc, mode); in dce_v10_0_encoder_mode_set()
3365 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_encoder_prepare()
3369 if ((amdgpu_encoder->active_device & in dce_v10_0_encoder_prepare()
3373 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_prepare()
3375 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); in dce_v10_0_encoder_prepare()
3376 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v10_0_encoder_prepare()
3377 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3387 if (amdgpu_connector->router.cd_valid) in dce_v10_0_encoder_prepare()
3391 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v10_0_encoder_prepare()
3404 struct drm_device *dev = encoder->dev; in dce_v10_0_encoder_commit()
3422 dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_disable()
3423 dig->dig_encoder = -1; in dce_v10_0_encoder_disable()
3425 amdgpu_encoder->active_device = 0; in dce_v10_0_encoder_disable()
3489 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_destroy()
3491 kfree(amdgpu_encoder->enc_priv); in dce_v10_0_encoder_destroy()
3510 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_encoder_add()
3512 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v10_0_encoder_add()
3513 amdgpu_encoder->devices |= supported_device; in dce_v10_0_encoder_add()
3524 encoder = &amdgpu_encoder->base; in dce_v10_0_encoder_add()
3525 switch (adev->mode_info.num_crtc) { in dce_v10_0_encoder_add()
3527 encoder->possible_crtcs = 0x1; in dce_v10_0_encoder_add()
3531 encoder->possible_crtcs = 0x3; in dce_v10_0_encoder_add()
3534 encoder->possible_crtcs = 0xf; in dce_v10_0_encoder_add()
3537 encoder->possible_crtcs = 0x3f; in dce_v10_0_encoder_add()
3541 amdgpu_encoder->enc_priv = NULL; in dce_v10_0_encoder_add()
3543 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v10_0_encoder_add()
3544 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v10_0_encoder_add()
3545 amdgpu_encoder->devices = supported_device; in dce_v10_0_encoder_add()
3546 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v10_0_encoder_add()
3547 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v10_0_encoder_add()
3548 amdgpu_encoder->is_ext_encoder = false; in dce_v10_0_encoder_add()
3549 amdgpu_encoder->caps = caps; in dce_v10_0_encoder_add()
3551 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_encoder_add()
3563 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v10_0_encoder_add()
3564 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v10_0_encoder_add()
3567 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3568 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v10_0_encoder_add()
3571 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3575 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3589 amdgpu_encoder->is_ext_encoder = true; in dce_v10_0_encoder_add()
3590 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_add()
3593 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v10_0_encoder_add()
3620 adev->mode_info.funcs = &dce_v10_0_display_funcs; in dce_v10_0_set_display_funcs()
3640 if (adev->mode_info.num_crtc > 0) in dce_v10_0_set_irq_funcs()
3641 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3643 adev->crtc_irq.num_types = 0; in dce_v10_0_set_irq_funcs()
3644 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; in dce_v10_0_set_irq_funcs()
3646 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3647 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; in dce_v10_0_set_irq_funcs()
3649 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v10_0_set_irq_funcs()
3650 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; in dce_v10_0_set_irq_funcs()