Lines Matching refs:lvds

1975 	struct amdgpu_encoder_atom_dig *lvds = NULL;  in amdgpu_atombios_encoder_get_lcd_info()  local
1982 lvds = in amdgpu_atombios_encoder_get_lcd_info()
1985 if (!lvds) in amdgpu_atombios_encoder_get_lcd_info()
1988 lvds->native_mode.clock = in amdgpu_atombios_encoder_get_lcd_info()
1990 lvds->native_mode.hdisplay = in amdgpu_atombios_encoder_get_lcd_info()
1992 lvds->native_mode.vdisplay = in amdgpu_atombios_encoder_get_lcd_info()
1994 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
1996 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()
1998 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in amdgpu_atombios_encoder_get_lcd_info()
2000 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()
2002 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()
2004 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + in amdgpu_atombios_encoder_get_lcd_info()
2006 lvds->panel_pwr_delay = in amdgpu_atombios_encoder_get_lcd_info()
2008 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; in amdgpu_atombios_encoder_get_lcd_info()
2012 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; in amdgpu_atombios_encoder_get_lcd_info()
2014 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; in amdgpu_atombios_encoder_get_lcd_info()
2016 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; in amdgpu_atombios_encoder_get_lcd_info()
2018 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; in amdgpu_atombios_encoder_get_lcd_info()
2020 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; in amdgpu_atombios_encoder_get_lcd_info()
2022 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); in amdgpu_atombios_encoder_get_lcd_info()
2023 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); in amdgpu_atombios_encoder_get_lcd_info()
2026 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); in amdgpu_atombios_encoder_get_lcd_info()
2028 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; in amdgpu_atombios_encoder_get_lcd_info()
2030 encoder->native_mode = lvds->native_mode; in amdgpu_atombios_encoder_get_lcd_info()
2033 lvds->linkb = true; in amdgpu_atombios_encoder_get_lcd_info()
2035 lvds->linkb = false; in amdgpu_atombios_encoder_get_lcd_info()
2089 lvds->native_mode.width_mm = panel_res_record->usHSize; in amdgpu_atombios_encoder_get_lcd_info()
2090 lvds->native_mode.height_mm = panel_res_record->usVSize; in amdgpu_atombios_encoder_get_lcd_info()
2103 return lvds; in amdgpu_atombios_encoder_get_lcd_info()