503 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_update_vs_emph()  argument
506 	amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,  in amdgpu_atombios_dp_update_vs_emph()
508 					       0, dp_info->train_set[0]); /* sets all lanes at once */  in amdgpu_atombios_dp_update_vs_emph()
511 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in amdgpu_atombios_dp_update_vs_emph()
512 			  dp_info->train_set, dp_info->dp_lane_count);  in amdgpu_atombios_dp_update_vs_emph()
516 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)  in amdgpu_atombios_dp_set_tp()  argument
532 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);  in amdgpu_atombios_dp_set_tp()
535 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in amdgpu_atombios_dp_set_tp()
539 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_init()  argument
541 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);  in amdgpu_atombios_dp_link_train_init()
546 	amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in amdgpu_atombios_dp_link_train_init()
549 	if (dp_info->dpcd[3] & 0x1)  in amdgpu_atombios_dp_link_train_init()
550 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
553 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
557 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in amdgpu_atombios_dp_link_train_init()
560 	tmp = dp_info->dp_lane_count;  in amdgpu_atombios_dp_link_train_init()
561 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in amdgpu_atombios_dp_link_train_init()
563 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
566 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in amdgpu_atombios_dp_link_train_init()
567 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
570 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_init()
574 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
582 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_finish()  argument
587 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_finish()
592 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_finish()
599 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_cr()  argument
605 	amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);  in amdgpu_atombios_dp_link_train_cr()
606 	memset(dp_info->train_set, 0, 4);  in amdgpu_atombios_dp_link_train_cr()
607 	amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
613 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
616 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);  in amdgpu_atombios_dp_link_train_cr()
618 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_cr()
619 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_cr()
624 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_cr()
629 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in amdgpu_atombios_dp_link_train_cr()
630 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in amdgpu_atombios_dp_link_train_cr()
633 		if (i == dp_info->dp_lane_count) {  in amdgpu_atombios_dp_link_train_cr()
638 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in amdgpu_atombios_dp_link_train_cr()
639 			++dp_info->tries;  in amdgpu_atombios_dp_link_train_cr()
640 			if (dp_info->tries == 5) {  in amdgpu_atombios_dp_link_train_cr()
645 			dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
647 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in amdgpu_atombios_dp_link_train_cr()
650 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_cr()
651 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_cr()
653 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
660 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_cr()
661 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in amdgpu_atombios_dp_link_train_cr()
668 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_ce()  argument
672 	if (dp_info->tp3_supported)  in amdgpu_atombios_dp_link_train_ce()
673 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);  in amdgpu_atombios_dp_link_train_ce()
675 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);  in amdgpu_atombios_dp_link_train_ce()
678 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_ce()
681 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);  in amdgpu_atombios_dp_link_train_ce()
683 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_ce()
684 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_ce()
689 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_ce()
695 		if (dp_info->tries > 5) {  in amdgpu_atombios_dp_link_train_ce()
701 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_ce()
702 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_ce()
704 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_ce()
705 		dp_info->tries++;  in amdgpu_atombios_dp_link_train_ce()
713 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_ce()
714 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in amdgpu_atombios_dp_link_train_ce()
728 	struct amdgpu_atombios_dp_link_train_info dp_info;  in amdgpu_atombios_dp_link_train()  local
746 			dp_info.tp3_supported = true;  in amdgpu_atombios_dp_link_train()
748 			dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
750 		dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
753 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in amdgpu_atombios_dp_link_train()
754 	dp_info.adev = adev;  in amdgpu_atombios_dp_link_train()
755 	dp_info.encoder = encoder;  in amdgpu_atombios_dp_link_train()
756 	dp_info.connector = connector;  in amdgpu_atombios_dp_link_train()
757 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in amdgpu_atombios_dp_link_train()
758 	dp_info.dp_clock = dig_connector->dp_clock;  in amdgpu_atombios_dp_link_train()
759 	dp_info.aux = &amdgpu_connector->ddc_bus->aux;  in amdgpu_atombios_dp_link_train()
761 	if (amdgpu_atombios_dp_link_train_init(&dp_info))  in amdgpu_atombios_dp_link_train()
763 	if (amdgpu_atombios_dp_link_train_cr(&dp_info))  in amdgpu_atombios_dp_link_train()
765 	if (amdgpu_atombios_dp_link_train_ce(&dp_info))  in amdgpu_atombios_dp_link_train()
768 	if (amdgpu_atombios_dp_link_train_finish(&dp_info))  in amdgpu_atombios_dp_link_train()