Lines Matching +full:mode +full:- +full:switch
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
39 struct drm_display_mode *mode, in amdgpu_atombios_crtc_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
65 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup()
66 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in amdgpu_atombios_crtc_overscan_setup()
68 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup()
69 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in amdgpu_atombios_crtc_overscan_setup()
74 args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border); in amdgpu_atombios_crtc_overscan_setup()
75 args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border); in amdgpu_atombios_crtc_overscan_setup()
76 args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border); in amdgpu_atombios_crtc_overscan_setup()
77 args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border); in amdgpu_atombios_crtc_overscan_setup()
80 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_overscan_setup()
85 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_scaler_setup()
93 args.ucScaler = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_scaler_setup()
95 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_scaler_setup()
109 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_scaler_setup()
115 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_lock()
123 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_lock()
126 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_lock()
132 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_enable()
139 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_enable()
142 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_enable()
148 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_blank()
155 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_blank()
158 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_blank()
164 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_powergate()
171 args.ucDispPipeId = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_powergate()
174 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_powergate()
186 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_powergate_init()
190 struct drm_display_mode *mode) in amdgpu_atombios_crtc_set_dtd_timing() argument
193 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_set_dtd_timing()
200 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
202 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
203 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
205 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
207 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border); in amdgpu_atombios_crtc_set_dtd_timing()
209 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in amdgpu_atombios_crtc_set_dtd_timing()
211 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border); in amdgpu_atombios_crtc_set_dtd_timing()
213 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in amdgpu_atombios_crtc_set_dtd_timing()
214 args.ucH_Border = amdgpu_crtc->h_border; in amdgpu_atombios_crtc_set_dtd_timing()
215 args.ucV_Border = amdgpu_crtc->v_border; in amdgpu_atombios_crtc_set_dtd_timing()
217 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
219 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
221 if (mode->flags & DRM_MODE_FLAG_CSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
223 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in amdgpu_atombios_crtc_set_dtd_timing()
225 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in amdgpu_atombios_crtc_set_dtd_timing()
229 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_set_dtd_timing()
231 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_set_dtd_timing()
256 if (ss->percentage == 0) in amdgpu_atombios_crtc_program_ss()
258 if (ss->type & ATOM_EXTERNAL_SS_MASK) in amdgpu_atombios_crtc_program_ss()
261 for (i = 0; i < adev->mode_info.num_crtc; i++) { in amdgpu_atombios_crtc_program_ss()
262 if (adev->mode_info.crtcs[i] && in amdgpu_atombios_crtc_program_ss()
263 adev->mode_info.crtcs[i]->enabled && in amdgpu_atombios_crtc_program_ss()
265 pll_id == adev->mode_info.crtcs[i]->pll_id) { in amdgpu_atombios_crtc_program_ss()
278 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in amdgpu_atombios_crtc_program_ss()
279 switch (pll_id) { in amdgpu_atombios_crtc_program_ss()
292 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in amdgpu_atombios_crtc_program_ss()
293 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in amdgpu_atombios_crtc_program_ss()
296 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_program_ss()
305 struct drm_display_mode *mode) in amdgpu_atombios_crtc_adjust_pll() argument
308 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_adjust_pll()
310 struct drm_encoder *encoder = amdgpu_crtc->encoder; in amdgpu_atombios_crtc_adjust_pll()
313 u32 adjusted_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
315 u32 dp_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
316 u32 clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
317 int bpc = amdgpu_crtc->bpc; in amdgpu_atombios_crtc_adjust_pll()
318 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock); in amdgpu_atombios_crtc_adjust_pll()
323 amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
325 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in amdgpu_atombios_crtc_adjust_pll()
330 amdgpu_connector->con_priv; in amdgpu_atombios_crtc_adjust_pll()
332 dp_clock = dig_connector->dp_clock; in amdgpu_atombios_crtc_adjust_pll()
337 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in amdgpu_atombios_crtc_adjust_pll()
338 if (amdgpu_crtc->ss_enabled) { in amdgpu_atombios_crtc_adjust_pll()
339 if (amdgpu_crtc->ss.refdiv) { in amdgpu_atombios_crtc_adjust_pll()
340 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; in amdgpu_atombios_crtc_adjust_pll()
341 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; in amdgpu_atombios_crtc_adjust_pll()
342 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
347 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ in amdgpu_atombios_crtc_adjust_pll()
348 if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in amdgpu_atombios_crtc_adjust_pll()
349 adjusted_clock = mode->clock * 2; in amdgpu_atombios_crtc_adjust_pll()
350 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in amdgpu_atombios_crtc_adjust_pll()
351 amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER; in amdgpu_atombios_crtc_adjust_pll()
352 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in amdgpu_atombios_crtc_adjust_pll()
353 amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD; in amdgpu_atombios_crtc_adjust_pll()
358 switch (bpc) { in amdgpu_atombios_crtc_adjust_pll()
379 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_adjust_pll()
385 switch (frev) { in amdgpu_atombios_crtc_adjust_pll()
387 switch (crev) { in amdgpu_atombios_crtc_adjust_pll()
391 args.v1.ucTransmitterID = amdgpu_encoder->encoder_id; in amdgpu_atombios_crtc_adjust_pll()
393 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) in amdgpu_atombios_crtc_adjust_pll()
397 amdgpu_atom_execute_table(adev->mode_info.atom_context, in amdgpu_atombios_crtc_adjust_pll()
403 args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; in amdgpu_atombios_crtc_adjust_pll()
406 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) in amdgpu_atombios_crtc_adjust_pll()
414 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in amdgpu_atombios_crtc_adjust_pll()
415 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_crtc_adjust_pll()
416 if (dig->coherent_mode) in amdgpu_atombios_crtc_adjust_pll()
430 amdgpu_atom_execute_table(adev->mode_info.atom_context, in amdgpu_atombios_crtc_adjust_pll()
434 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
435 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; in amdgpu_atombios_crtc_adjust_pll()
436 amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in amdgpu_atombios_crtc_adjust_pll()
439 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
440 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV; in amdgpu_atombios_crtc_adjust_pll()
441 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in amdgpu_atombios_crtc_adjust_pll()
480 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_set_disp_eng_pll()
484 switch (frev) { in amdgpu_atombios_crtc_set_disp_eng_pll()
486 switch (crev) { in amdgpu_atombios_crtc_set_disp_eng_pll()
500 if (adev->asic_type == CHIP_TAHITI || in amdgpu_atombios_crtc_set_disp_eng_pll()
501 adev->asic_type == CHIP_PITCAIRN || in amdgpu_atombios_crtc_set_disp_eng_pll()
502 adev->asic_type == CHIP_VERDE || in amdgpu_atombios_crtc_set_disp_eng_pll()
503 adev->asic_type == CHIP_OLAND) in amdgpu_atombios_crtc_set_disp_eng_pll()
517 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_set_disp_eng_pll()
536 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_set_dce_clock()
540 switch (frev) { in amdgpu_atombios_crtc_set_dce_clock()
542 switch (crev) { in amdgpu_atombios_crtc_set_dce_clock()
547 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_set_dce_clock()
589 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_program_pll()
597 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_program_pll()
601 switch (frev) { in amdgpu_atombios_crtc_program_pll()
603 switch (crev) { in amdgpu_atombios_crtc_program_pll()
637 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in amdgpu_atombios_crtc_program_pll()
650 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && in amdgpu_atombios_crtc_program_pll()
654 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
680 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && in amdgpu_atombios_crtc_program_pll()
685 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
713 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
743 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_crtc_program_pll()
747 struct drm_display_mode *mode) in amdgpu_atombios_crtc_prepare_pll() argument
750 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_prepare_pll()
753 to_amdgpu_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
754 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
756 amdgpu_crtc->bpc = 8; in amdgpu_atombios_crtc_prepare_pll()
757 amdgpu_crtc->ss_enabled = false; in amdgpu_atombios_crtc_prepare_pll()
759 if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in amdgpu_atombios_crtc_prepare_pll()
760 (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in amdgpu_atombios_crtc_prepare_pll()
761 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_crtc_prepare_pll()
763 amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
767 amdgpu_connector->con_priv; in amdgpu_atombios_crtc_prepare_pll()
770 /* Assign mode clock for hdmi deep color max clock limit check */ in amdgpu_atombios_crtc_prepare_pll()
771 amdgpu_connector->pixelclock_for_modeset = mode->clock; in amdgpu_atombios_crtc_prepare_pll()
772 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector); in amdgpu_atombios_crtc_prepare_pll()
774 switch (encoder_mode) { in amdgpu_atombios_crtc_prepare_pll()
778 dp_clock = dig_connector->dp_clock / 10; in amdgpu_atombios_crtc_prepare_pll()
779 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
780 amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
785 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
787 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
788 dig->lcd_ss_id, in amdgpu_atombios_crtc_prepare_pll()
789 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
792 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
794 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
796 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
799 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
801 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
803 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
811 amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode); in amdgpu_atombios_crtc_prepare_pll()
816 void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) in amdgpu_atombios_crtc_set_pll() argument
819 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_set_pll()
822 to_amdgpu_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_set_pll()
823 u32 pll_clock = mode->clock; in amdgpu_atombios_crtc_set_pll()
824 u32 clock = mode->clock; in amdgpu_atombios_crtc_set_pll()
827 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_set_pll()
831 (amdgpu_crtc->bpc > 8)) in amdgpu_atombios_crtc_set_pll()
832 clock = amdgpu_crtc->adjusted_clock; in amdgpu_atombios_crtc_set_pll()
834 switch (amdgpu_crtc->pll_id) { in amdgpu_atombios_crtc_set_pll()
836 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
839 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
844 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
849 pll->flags = amdgpu_crtc->pll_flags; in amdgpu_atombios_crtc_set_pll()
850 pll->reference_div = amdgpu_crtc->pll_reference_div; in amdgpu_atombios_crtc_set_pll()
851 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
853 amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock, in amdgpu_atombios_crtc_set_pll()
856 amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
857 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()
859 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
860 encoder_mode, amdgpu_encoder->encoder_id, clock, in amdgpu_atombios_crtc_set_pll()
862 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()
864 if (amdgpu_crtc->ss_enabled) { in amdgpu_atombios_crtc_set_pll()
868 (u32)amdgpu_crtc->ss.percentage) / in amdgpu_atombios_crtc_set_pll()
869 (100 * (u32)amdgpu_crtc->ss.percentage_divider); in amdgpu_atombios_crtc_set_pll()
870 amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in amdgpu_atombios_crtc_set_pll()
871 amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in amdgpu_atombios_crtc_set_pll()
873 if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in amdgpu_atombios_crtc_set_pll()
874 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
875 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
877 step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
878 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
879 amdgpu_crtc->ss.step = step_size; in amdgpu_atombios_crtc_set_pll()
881 amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
882 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()