817 	pcie_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_pcie_state()
818 	pcie_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_pcie_state()
819 	pcie_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_pcie_state()
820 	pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE;  in aqua_vanjaram_read_pcie_state()
821 	pcie_reg_state->common_header.num_instances = 1;  in aqua_vanjaram_read_pcie_state()
823 	return pcie_reg_state->common_header.structure_size;  in aqua_vanjaram_read_pcie_state()
901 	xgmi_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_xgmi_state()
902 	xgmi_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_xgmi_state()
903 	xgmi_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_xgmi_state()
904 	xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI;  in aqua_vanjaram_read_xgmi_state()
905 	xgmi_reg_state->common_header.num_instances = max_xgmi_instances;  in aqua_vanjaram_read_xgmi_state()
907 	return xgmi_reg_state->common_header.structure_size;  in aqua_vanjaram_read_xgmi_state()
974 	wafl_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_wafl_state()
975 	wafl_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_wafl_state()
976 	wafl_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_wafl_state()
977 	wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL;  in aqua_vanjaram_read_wafl_state()
978 	wafl_reg_state->common_header.num_instances = max_wafl_instances;  in aqua_vanjaram_read_wafl_state()
980 	return wafl_reg_state->common_header.structure_size;  in aqua_vanjaram_read_wafl_state()
1093 	usr_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_usr_state()
1094 	usr_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_usr_state()
1095 	usr_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_usr_state()
1096 	usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR;  in aqua_vanjaram_read_usr_state()
1097 	usr_reg_state->common_header.num_instances = max_usr_instances;  in aqua_vanjaram_read_usr_state()
1099 	return usr_reg_state->common_header.structure_size;  in aqua_vanjaram_read_usr_state()