Lines Matching defs:amdgpu_rlc
260 struct amdgpu_rlc { struct
281 const struct amdgpu_rlc_funcs *funcs; argument
284 u32 save_and_restore_offset;
285 u32 clear_state_descriptor_offset;
286 u32 avail_scratch_ram_locations;
287 u32 reg_restore_list_size;
288 u32 reg_list_format_start;
289 u32 reg_list_format_separate_start;
290 u32 starting_offsets_start;
291 u32 reg_list_format_size_bytes;
292 u32 reg_list_size_bytes;
293 u32 reg_list_format_direct_reg_list_length;
294 u32 save_restore_list_cntl_size_bytes;
295 u32 save_restore_list_gpm_size_bytes;
296 u32 save_restore_list_srm_size_bytes;
297 u32 rlc_iram_ucode_size_bytes;
298 u32 rlc_dram_ucode_size_bytes;
299 u32 rlcp_ucode_size_bytes;
300 u32 rlcv_ucode_size_bytes;
301 u32 global_tap_delays_ucode_size_bytes;
302 u32 se0_tap_delays_ucode_size_bytes;
303 u32 se1_tap_delays_ucode_size_bytes;
304 u32 se2_tap_delays_ucode_size_bytes;
305 u32 se3_tap_delays_ucode_size_bytes;
307 u32 *register_list_format;
308 u32 *register_restore;
309 u8 *save_restore_list_cntl;
310 u8 *save_restore_list_gpm;
311 u8 *save_restore_list_srm;
312 u8 *rlc_iram_ucode;
336 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; argument