2  * Copyright 2016 Advanced Micro Devices, Inc.
312 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
313 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib…
314 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
315 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
316 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
317 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
318 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
319 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
320 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
321 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
322 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (fla…
323 …g_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), …  argument
324 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
325 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
326 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
327 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (…
328 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
329 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
330 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
331 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r…
332 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
333 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
334 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
335 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
336 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
337 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
338 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
339 #define amdgpu_ring_reset(r, v) (r)->funcs->reset((r), (v))
367 	*ring->cond_exe_cpu_addr = cond_exec;  in amdgpu_ring_set_preempt_cond_exec()
373 	while (i <= ring->buf_mask)  in amdgpu_ring_clear_ring()
374 		ring->ring[i++] = ring->funcs->nop;  in amdgpu_ring_clear_ring()
380 	if (ring->count_dw <= 0)  in amdgpu_ring_write()
382 	ring->ring[ring->wptr++ & ring->buf_mask] = v;  in amdgpu_ring_write()
383 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write()
384 	ring->count_dw--;  in amdgpu_ring_write()
393 	if (unlikely(ring->count_dw < count_dw))  in amdgpu_ring_write_multiple()
396 	occupied = ring->wptr & ring->buf_mask;  in amdgpu_ring_write_multiple()
397 	dst = (void *)&ring->ring[occupied];  in amdgpu_ring_write_multiple()
398 	chunk1 = ring->buf_mask + 1 - occupied;  in amdgpu_ring_write_multiple()
400 	chunk2 = count_dw - chunk1;  in amdgpu_ring_write_multiple()
409 		dst = (void *)ring->ring;  in amdgpu_ring_write_multiple()
413 	ring->wptr += count_dw;  in amdgpu_ring_write_multiple()
414 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write_multiple()
415 	ring->count_dw -= count_dw;  in amdgpu_ring_write_multiple()
419  * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
430 	if (!ring->funcs->init_cond_exec)  in amdgpu_ring_patch_cond_exec()
433 	WARN_ON(offset > ring->buf_mask);  in amdgpu_ring_patch_cond_exec()
434 	WARN_ON(ring->ring[offset] != 0);  in amdgpu_ring_patch_cond_exec()
436 	cur = (ring->wptr - 1) & ring->buf_mask;  in amdgpu_ring_patch_cond_exec()
438 		cur += ring->ring_size >> 2;  in amdgpu_ring_patch_cond_exec()
439 	ring->ring[offset] = cur - offset;  in amdgpu_ring_patch_cond_exec()
443 	(ring->is_mes_queue && ring->mes_ctx ?				\
444 	 (ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
447 	(ring->is_mes_queue && ring->mes_ctx ?				\
448 	 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
460 	return ib->ptr[idx];  in amdgpu_ib_get_value()
466 	ib->ptr[idx] = value;  in amdgpu_ib_set_value()