16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
33  * amdgpu_pll_reduce_ratio - fractional number reduction
70  * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
75  * @post_div: post divider
76  * @fb_div_max: feedback divider maximum
77  * @ref_div_max: reference divider maximum
78  * @fb_div: resulting feedback divider
79  * @ref_div: resulting reference divider
81  * Calculate feedback and reference divider for a given post divider. Makes
90 	/* limit reference * post divider to a maximum */  in amdgpu_pll_get_fb_ref_div()
91 	if (adev->family == AMDGPU_FAMILY_SI)  in amdgpu_pll_get_fb_ref_div()
96 	/* get matching reference and feedback divider */  in amdgpu_pll_get_fb_ref_div()
100 	/* limit fb divider to its maximum */  in amdgpu_pll_get_fb_ref_div()
108  * amdgpu_pll_compute - compute PLL paramaters
114  * @fb_div_p: resulting feedback divider
115  * @frac_fb_div_p: fractional part of the feedback divider
116  * @ref_div_p: resulting reference divider
117  * @post_div_p: resulting reference divider
131 	unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?  in amdgpu_pll_compute()
140 	/* determine allowed feedback divider range */  in amdgpu_pll_compute()
141 	fb_div_min = pll->min_feedback_div;  in amdgpu_pll_compute()
142 	fb_div_max = pll->max_feedback_div;  in amdgpu_pll_compute()
144 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
149 	/* determine allowed ref divider range */  in amdgpu_pll_compute()
150 	if (pll->flags & AMDGPU_PLL_USE_REF_DIV)  in amdgpu_pll_compute()
151 		ref_div_min = pll->reference_div;  in amdgpu_pll_compute()
153 		ref_div_min = pll->min_ref_div;  in amdgpu_pll_compute()
155 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&  in amdgpu_pll_compute()
156 	    pll->flags & AMDGPU_PLL_USE_REF_DIV)  in amdgpu_pll_compute()
157 		ref_div_max = pll->reference_div;  in amdgpu_pll_compute()
159 		ref_div_max = pll->max_ref_div;  in amdgpu_pll_compute()
161 	/* determine allowed post divider range */  in amdgpu_pll_compute()
162 	if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {  in amdgpu_pll_compute()
163 		post_div_min = pll->post_div;  in amdgpu_pll_compute()
164 		post_div_max = pll->post_div;  in amdgpu_pll_compute()
168 		if (pll->flags & AMDGPU_PLL_IS_LCD) {  in amdgpu_pll_compute()
169 			vco_min = pll->lcd_pll_out_min;  in amdgpu_pll_compute()
170 			vco_max = pll->lcd_pll_out_max;  in amdgpu_pll_compute()
172 			vco_min = pll->pll_out_min;  in amdgpu_pll_compute()
173 			vco_max = pll->pll_out_max;  in amdgpu_pll_compute()
176 		if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
184 		if (post_div_min < pll->min_post_div)  in amdgpu_pll_compute()
185 			post_div_min = pll->min_post_div;  in amdgpu_pll_compute()
189 			--post_div_max;  in amdgpu_pll_compute()
190 		if (post_div_max > pll->max_post_div)  in amdgpu_pll_compute()
191 			post_div_max = pll->max_post_div;  in amdgpu_pll_compute()
196 	den = pll->reference_freq;  in amdgpu_pll_compute()
201 	/* now search for a post divider */  in amdgpu_pll_compute()
202 	if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)  in amdgpu_pll_compute()
212 		diff = abs(target_clock - (pll->reference_freq * fb_div) /  in amdgpu_pll_compute()
216 		    !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {  in amdgpu_pll_compute()
224 	/* get the feedback and reference divider for the optimal value */  in amdgpu_pll_compute()
229 	/* this also makes sure that the reference divider is large enough */  in amdgpu_pll_compute()
233 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {  in amdgpu_pll_compute()
234 		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);  in amdgpu_pll_compute()
243 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
251 	*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +  in amdgpu_pll_compute()
252 			(pll->reference_freq * *frac_fb_div_p)) /  in amdgpu_pll_compute()
257 	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",  in amdgpu_pll_compute()
263  * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
271 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_use_mask()
276 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_use_mask()
281 		if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_use_mask()
282 			pll_in_use |= (1 << test_amdgpu_crtc->pll_id);  in amdgpu_pll_get_use_mask()
288  * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
298 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_shared_dp_ppll()
302 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_shared_dp_ppll()
306 		if (test_amdgpu_crtc->encoder &&  in amdgpu_pll_get_shared_dp_ppll()
307 		    ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {  in amdgpu_pll_get_shared_dp_ppll()
309 			if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_shared_dp_ppll()
310 				return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_dp_ppll()
317  * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
321  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
327 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_shared_nondp_ppll()
332 	adjusted_clock = amdgpu_crtc->adjusted_clock;  in amdgpu_pll_get_shared_nondp_ppll()
337 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_shared_nondp_ppll()
341 		if (test_amdgpu_crtc->encoder &&  in amdgpu_pll_get_shared_nondp_ppll()
342 		    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {  in amdgpu_pll_get_shared_nondp_ppll()
344 			if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {  in amdgpu_pll_get_shared_nondp_ppll()
346 				if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_shared_nondp_ppll()
347 					return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_nondp_ppll()
349 			/* for non-DP check the clock */  in amdgpu_pll_get_shared_nondp_ppll()
350 			test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;  in amdgpu_pll_get_shared_nondp_ppll()
351 			if ((crtc->mode.clock == test_crtc->mode.clock) &&  in amdgpu_pll_get_shared_nondp_ppll()
353 			    (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&  in amdgpu_pll_get_shared_nondp_ppll()
354 			    (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))  in amdgpu_pll_get_shared_nondp_ppll()
355 				return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_nondp_ppll()