Lines Matching +full:x +full:- +full:min
58 if (gpu_instance->adev == adev) { in amdgpu_unregister_gpu_instance()
60 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; in amdgpu_unregister_gpu_instance()
61 mgpu_info.num_gpu--; in amdgpu_unregister_gpu_instance()
62 if (adev->flags & AMD_IS_APU) in amdgpu_unregister_gpu_instance()
63 mgpu_info.num_apu--; in amdgpu_unregister_gpu_instance()
65 mgpu_info.num_dgpu--; in amdgpu_unregister_gpu_instance()
74 * amdgpu_driver_unload_kms - Main unload function for KMS.
90 if (adev->rmmio == NULL) in amdgpu_driver_unload_kms()
113 gpu_instance->adev = adev; in amdgpu_register_gpu_instance()
114 gpu_instance->mgpu_fan_enabled = 0; in amdgpu_register_gpu_instance()
117 if (adev->flags & AMD_IS_APU) in amdgpu_register_gpu_instance()
126 * amdgpu_driver_load_kms - Main load function for KMS.
149 dev_err(dev->dev, "Fatal error during GPU init\n"); in amdgpu_driver_load_kms()
161 dev_dbg(dev->dev, "Error during ACPI methods call\n"); in amdgpu_driver_load_kms()
215 switch (query_fw->fw_type) { in amdgpu_firmware_info()
217 fw_info->ver = adev->vce.fw_version; in amdgpu_firmware_info()
218 fw_info->feature = adev->vce.fb_version; in amdgpu_firmware_info()
221 fw_info->ver = adev->uvd.fw_version; in amdgpu_firmware_info()
222 fw_info->feature = 0; in amdgpu_firmware_info()
225 fw_info->ver = adev->vcn.fw_version; in amdgpu_firmware_info()
226 fw_info->feature = 0; in amdgpu_firmware_info()
229 fw_info->ver = adev->gmc.fw_version; in amdgpu_firmware_info()
230 fw_info->feature = 0; in amdgpu_firmware_info()
233 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
234 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
237 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
238 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
241 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
242 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
245 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
246 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
249 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
250 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
253 fw_info->ver = adev->gfx.rlc_srlg_fw_version; in amdgpu_firmware_info()
254 fw_info->feature = adev->gfx.rlc_srlg_feature_version; in amdgpu_firmware_info()
257 fw_info->ver = adev->gfx.rlc_srls_fw_version; in amdgpu_firmware_info()
258 fw_info->feature = adev->gfx.rlc_srls_feature_version; in amdgpu_firmware_info()
261 fw_info->ver = adev->gfx.rlcp_ucode_version; in amdgpu_firmware_info()
262 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; in amdgpu_firmware_info()
265 fw_info->ver = adev->gfx.rlcv_ucode_version; in amdgpu_firmware_info()
266 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; in amdgpu_firmware_info()
269 if (query_fw->index == 0) { in amdgpu_firmware_info()
270 fw_info->ver = adev->gfx.mec_fw_version; in amdgpu_firmware_info()
271 fw_info->feature = adev->gfx.mec_feature_version; in amdgpu_firmware_info()
272 } else if (query_fw->index == 1) { in amdgpu_firmware_info()
273 fw_info->ver = adev->gfx.mec2_fw_version; in amdgpu_firmware_info()
274 fw_info->feature = adev->gfx.mec2_feature_version; in amdgpu_firmware_info()
276 return -EINVAL; in amdgpu_firmware_info()
279 fw_info->ver = adev->pm.fw_version; in amdgpu_firmware_info()
280 fw_info->feature = 0; in amdgpu_firmware_info()
283 switch (query_fw->index) { in amdgpu_firmware_info()
285 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
286 fw_info->feature = adev->psp.xgmi_context.context in amdgpu_firmware_info()
290 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
291 fw_info->feature = adev->psp.ras_context.context in amdgpu_firmware_info()
295 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
296 fw_info->feature = adev->psp.hdcp_context.context in amdgpu_firmware_info()
300 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
301 fw_info->feature = adev->psp.dtm_context.context in amdgpu_firmware_info()
305 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
306 fw_info->feature = adev->psp.rap_context.context in amdgpu_firmware_info()
310 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; in amdgpu_firmware_info()
311 fw_info->feature = in amdgpu_firmware_info()
312 adev->psp.securedisplay_context.context.bin_desc in amdgpu_firmware_info()
316 return -EINVAL; in amdgpu_firmware_info()
320 if (query_fw->index >= adev->sdma.num_instances) in amdgpu_firmware_info()
321 return -EINVAL; in amdgpu_firmware_info()
322 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; in amdgpu_firmware_info()
323 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; in amdgpu_firmware_info()
326 fw_info->ver = adev->psp.sos.fw_version; in amdgpu_firmware_info()
327 fw_info->feature = adev->psp.sos.feature_version; in amdgpu_firmware_info()
330 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; in amdgpu_firmware_info()
331 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; in amdgpu_firmware_info()
334 fw_info->ver = adev->dm.dmcu_fw_version; in amdgpu_firmware_info()
335 fw_info->feature = 0; in amdgpu_firmware_info()
338 fw_info->ver = adev->dm.dmcub_fw_version; in amdgpu_firmware_info()
339 fw_info->feature = 0; in amdgpu_firmware_info()
342 fw_info->ver = adev->psp.toc.fw_version; in amdgpu_firmware_info()
343 fw_info->feature = adev->psp.toc.feature_version; in amdgpu_firmware_info()
346 fw_info->ver = adev->psp.cap_fw_version; in amdgpu_firmware_info()
347 fw_info->feature = adev->psp.cap_feature_version; in amdgpu_firmware_info()
350 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; in amdgpu_firmware_info()
351 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) in amdgpu_firmware_info()
355 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; in amdgpu_firmware_info()
356 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) in amdgpu_firmware_info()
360 fw_info->ver = adev->gfx.imu_fw_version; in amdgpu_firmware_info()
361 fw_info->feature = 0; in amdgpu_firmware_info()
364 fw_info->ver = adev->vpe.fw_version; in amdgpu_firmware_info()
365 fw_info->feature = adev->vpe.feature_version; in amdgpu_firmware_info()
368 return -EINVAL; in amdgpu_firmware_info()
383 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) in amdgpu_hw_ip_info()
384 return -EINVAL; in amdgpu_hw_ip_info()
386 switch (info->query_hw_ip.type) { in amdgpu_hw_ip_info()
389 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in amdgpu_hw_ip_info()
390 if (adev->gfx.gfx_ring[i].sched.ready) in amdgpu_hw_ip_info()
397 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_hw_ip_info()
398 if (adev->gfx.compute_ring[i].sched.ready) in amdgpu_hw_ip_info()
405 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_hw_ip_info()
406 if (adev->sdma.instance[i].ring.sched.ready) in amdgpu_hw_ip_info()
413 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
414 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
417 if (adev->uvd.inst[i].ring.sched.ready) in amdgpu_hw_ip_info()
425 for (i = 0; i < adev->vce.num_rings; i++) in amdgpu_hw_ip_info()
426 if (adev->vce.ring[i].sched.ready) in amdgpu_hw_ip_info()
433 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
434 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
437 for (j = 0; j < adev->uvd.num_enc_rings; j++) in amdgpu_hw_ip_info()
438 if (adev->uvd.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
447 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
450 if (adev->vcn.inst[i].ring_dec.sched.ready) in amdgpu_hw_ip_info()
458 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
459 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
462 for (j = 0; j < adev->vcn.num_enc_rings; j++) in amdgpu_hw_ip_info()
463 if (adev->vcn.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
473 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_hw_ip_info()
474 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
477 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) in amdgpu_hw_ip_info()
478 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) in amdgpu_hw_ip_info()
486 if (adev->vpe.ring.sched.ready) in amdgpu_hw_ip_info()
492 return -EINVAL; in amdgpu_hw_ip_info()
495 for (i = 0; i < adev->num_ip_blocks; i++) in amdgpu_hw_ip_info()
496 if (adev->ip_blocks[i].version->type == type && in amdgpu_hw_ip_info()
497 adev->ip_blocks[i].status.valid) in amdgpu_hw_ip_info()
500 if (i == adev->num_ip_blocks) in amdgpu_hw_ip_info()
503 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], in amdgpu_hw_ip_info()
506 result->hw_ip_version_major = adev->ip_blocks[i].version->major; in amdgpu_hw_ip_info()
507 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; in amdgpu_hw_ip_info()
509 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_hw_ip_info()
512 result->ip_discovery_version = in amdgpu_hw_ip_info()
516 result->ip_discovery_version = in amdgpu_hw_ip_info()
522 result->ip_discovery_version = in amdgpu_hw_ip_info()
526 result->ip_discovery_version = in amdgpu_hw_ip_info()
530 result->ip_discovery_version = in amdgpu_hw_ip_info()
534 result->ip_discovery_version = 0; in amdgpu_hw_ip_info()
538 result->ip_discovery_version = 0; in amdgpu_hw_ip_info()
540 result->capabilities_flags = 0; in amdgpu_hw_ip_info()
541 result->available_rings = (1 << num_rings) - 1; in amdgpu_hw_ip_info()
542 result->ib_start_alignment = ib_start_alignment; in amdgpu_hw_ip_info()
543 result->ib_size_alignment = ib_size_alignment; in amdgpu_hw_ip_info()
551 * amdgpu_info_ioctl - answer a device specific request.
560 * Returns 0 on success, -EINVAL on failure.
566 struct amdgpu_mode_info *minfo = &adev->mode_info; in amdgpu_info_ioctl()
567 void __user *out = (void __user *)(uintptr_t)info->return_pointer; in amdgpu_info_ioctl()
573 uint32_t size = info->return_size; in amdgpu_info_ioctl()
580 if (!info->return_size || !info->return_pointer) in amdgpu_info_ioctl()
581 return -EINVAL; in amdgpu_info_ioctl()
583 switch (info->query) { in amdgpu_info_ioctl()
585 ui32 = adev->accel_working; in amdgpu_info_ioctl()
586 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
588 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { in amdgpu_info_ioctl()
589 crtc = (struct drm_crtc *)minfo->crtcs[i]; in amdgpu_info_ioctl()
590 if (crtc && crtc->base.id == info->mode_crtc.id) { in amdgpu_info_ioctl()
593 ui32 = amdgpu_crtc->crtc_id; in amdgpu_info_ioctl()
599 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); in amdgpu_info_ioctl()
600 return -EINVAL; in amdgpu_info_ioctl()
602 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
611 return ret ? -EFAULT : 0; in amdgpu_info_ioctl()
614 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; in amdgpu_info_ioctl()
615 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); in amdgpu_info_ioctl()
618 if (!ip_block || !ip_block->status.valid) in amdgpu_info_ioctl()
619 return -EINVAL; in amdgpu_info_ioctl()
621 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && in amdgpu_info_ioctl()
622 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { in amdgpu_info_ioctl()
623 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; in amdgpu_info_ioctl()
641 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; in amdgpu_info_ioctl()
650 return -EINVAL; in amdgpu_info_ioctl()
653 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
662 count = adev->sdma.num_instances; in amdgpu_info_ioctl()
665 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; in amdgpu_info_ioctl()
668 count = adev->vcn.num_vcn_inst; in amdgpu_info_ioctl()
671 count = adev->uvd.num_uvd_inst; in amdgpu_info_ioctl()
681 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
685 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
690 if (info->query_fw.ip_instance != 0) in amdgpu_info_ioctl()
691 return -EINVAL; in amdgpu_info_ioctl()
693 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); in amdgpu_info_ioctl()
698 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; in amdgpu_info_ioctl()
701 ui64 = atomic64_read(&adev->num_bytes_moved); in amdgpu_info_ioctl()
702 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
704 ui64 = atomic64_read(&adev->num_evictions); in amdgpu_info_ioctl()
705 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
707 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); in amdgpu_info_ioctl()
708 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
710 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); in amdgpu_info_ioctl()
711 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
713 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); in amdgpu_info_ioctl()
714 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
716 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); in amdgpu_info_ioctl()
717 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
722 gds_info.compute_partition_size = adev->gds.gds_size; in amdgpu_info_ioctl()
723 gds_info.gds_total_size = adev->gds.gds_size; in amdgpu_info_ioctl()
724 gds_info.gws_per_compute_partition = adev->gds.gws_size; in amdgpu_info_ioctl()
725 gds_info.oa_per_compute_partition = adev->gds.oa_size; in amdgpu_info_ioctl()
727 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; in amdgpu_info_ioctl()
732 vram_gtt.vram_size = adev->gmc.real_vram_size - in amdgpu_info_ioctl()
733 atomic64_read(&adev->vram_pin_size) - in amdgpu_info_ioctl()
736 min(adev->gmc.visible_vram_size - in amdgpu_info_ioctl()
737 atomic64_read(&adev->visible_pin_size), in amdgpu_info_ioctl()
739 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; in amdgpu_info_ioctl()
740 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); in amdgpu_info_ioctl()
742 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; in amdgpu_info_ioctl()
747 &adev->mman.gtt_mgr.manager; in amdgpu_info_ioctl()
749 &adev->mman.vram_mgr.manager; in amdgpu_info_ioctl()
752 mem.vram.total_heap_size = adev->gmc.real_vram_size; in amdgpu_info_ioctl()
753 mem.vram.usable_heap_size = adev->gmc.real_vram_size - in amdgpu_info_ioctl()
754 atomic64_read(&adev->vram_pin_size) - in amdgpu_info_ioctl()
761 adev->gmc.visible_vram_size; in amdgpu_info_ioctl()
763 min(adev->gmc.visible_vram_size - in amdgpu_info_ioctl()
764 atomic64_read(&adev->visible_pin_size), in amdgpu_info_ioctl()
767 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); in amdgpu_info_ioctl()
771 mem.gtt.total_heap_size = gtt_man->size; in amdgpu_info_ioctl()
772 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - in amdgpu_info_ioctl()
773 atomic64_read(&adev->gart_pin_size); in amdgpu_info_ioctl()
778 min((size_t)size, sizeof(mem))) in amdgpu_info_ioctl()
779 ? -EFAULT : 0; in amdgpu_info_ioctl()
785 unsigned int se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl()
788 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl()
792 if (!down_read_trylock(&adev->reset_domain->sem)) in amdgpu_info_ioctl()
793 return -ENOENT; in amdgpu_info_ioctl()
801 ret = -EINVAL; in amdgpu_info_ioctl()
808 ret = -EINVAL; in amdgpu_info_ioctl()
812 if (info->read_mmr_reg.count > 128) { in amdgpu_info_ioctl()
813 ret = -EINVAL; in amdgpu_info_ioctl()
817 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); in amdgpu_info_ioctl()
819 ret = -ENOMEM; in amdgpu_info_ioctl()
823 alloc_size = info->read_mmr_reg.count * sizeof(*regs); in amdgpu_info_ioctl()
826 for (i = 0; i < info->read_mmr_reg.count; i++) { in amdgpu_info_ioctl()
828 info->read_mmr_reg.dword_offset + i, in amdgpu_info_ioctl()
830 DRM_DEBUG_KMS("unallowed offset %#x\n", in amdgpu_info_ioctl()
831 info->read_mmr_reg.dword_offset + i); in amdgpu_info_ioctl()
834 ret = -EFAULT; in amdgpu_info_ioctl()
839 n = copy_to_user(out, regs, min(size, alloc_size)); in amdgpu_info_ioctl()
841 ret = (n ? -EFAULT : 0); in amdgpu_info_ioctl()
843 up_read(&adev->reset_domain->sem); in amdgpu_info_ioctl()
853 return -ENOMEM; in amdgpu_info_ioctl()
855 dev_info->device_id = adev->pdev->device; in amdgpu_info_ioctl()
856 dev_info->chip_rev = adev->rev_id; in amdgpu_info_ioctl()
857 dev_info->external_rev = adev->external_rev_id; in amdgpu_info_ioctl()
858 dev_info->pci_rev = adev->pdev->revision; in amdgpu_info_ioctl()
859 dev_info->family = adev->family; in amdgpu_info_ioctl()
860 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
861 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
863 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; in amdgpu_info_ioctl()
864 if (adev->pm.dpm_enabled) { in amdgpu_info_ioctl()
865 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; in amdgpu_info_ioctl()
866 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; in amdgpu_info_ioctl()
867 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; in amdgpu_info_ioctl()
868 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; in amdgpu_info_ioctl()
870 dev_info->max_engine_clock = in amdgpu_info_ioctl()
871 dev_info->min_engine_clock = in amdgpu_info_ioctl()
872 adev->clock.default_sclk * 10; in amdgpu_info_ioctl()
873 dev_info->max_memory_clock = in amdgpu_info_ioctl()
874 dev_info->min_memory_clock = in amdgpu_info_ioctl()
875 adev->clock.default_mclk * 10; in amdgpu_info_ioctl()
877 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; in amdgpu_info_ioctl()
878 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
879 adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
880 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; in amdgpu_info_ioctl()
881 dev_info->ids_flags = 0; in amdgpu_info_ioctl()
882 if (adev->flags & AMD_IS_APU) in amdgpu_info_ioctl()
883 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; in amdgpu_info_ioctl()
884 if (adev->gfx.mcbp) in amdgpu_info_ioctl()
885 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; in amdgpu_info_ioctl()
887 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; in amdgpu_info_ioctl()
888 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) in amdgpu_info_ioctl()
889 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; in amdgpu_info_ioctl()
891 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
892 vm_size -= AMDGPU_VA_RESERVED_TOP; in amdgpu_info_ioctl()
895 if (adev->vce.fw_version && in amdgpu_info_ioctl()
896 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) in amdgpu_info_ioctl()
897 vm_size = min(vm_size, 1ULL << 40); in amdgpu_info_ioctl()
899 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; in amdgpu_info_ioctl()
900 dev_info->virtual_address_max = in amdgpu_info_ioctl()
901 min(vm_size, AMDGPU_GMC_HOLE_START); in amdgpu_info_ioctl()
904 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; in amdgpu_info_ioctl()
905 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; in amdgpu_info_ioctl()
907 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); in amdgpu_info_ioctl()
908 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
909 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); in amdgpu_info_ioctl()
910 dev_info->cu_active_number = adev->gfx.cu_info.number; in amdgpu_info_ioctl()
911 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; in amdgpu_info_ioctl()
912 dev_info->ce_ram_size = adev->gfx.ce_ram_size; in amdgpu_info_ioctl()
913 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], in amdgpu_info_ioctl()
914 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); in amdgpu_info_ioctl()
915 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], in amdgpu_info_ioctl()
916 sizeof(dev_info->cu_bitmap)); in amdgpu_info_ioctl()
917 dev_info->vram_type = adev->gmc.vram_type; in amdgpu_info_ioctl()
918 dev_info->vram_bit_width = adev->gmc.vram_width; in amdgpu_info_ioctl()
919 dev_info->vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
920 dev_info->gc_double_offchip_lds_buf = in amdgpu_info_ioctl()
921 adev->gfx.config.double_offchip_lds_buf; in amdgpu_info_ioctl()
922 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; in amdgpu_info_ioctl()
923 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; in amdgpu_info_ioctl()
924 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_info_ioctl()
925 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; in amdgpu_info_ioctl()
926 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; in amdgpu_info_ioctl()
927 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; in amdgpu_info_ioctl()
928 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; in amdgpu_info_ioctl()
930 if (adev->family >= AMDGPU_FAMILY_NV) in amdgpu_info_ioctl()
931 dev_info->pa_sc_tile_steering_override = in amdgpu_info_ioctl()
932 adev->gfx.config.pa_sc_tile_steering_override; in amdgpu_info_ioctl()
934 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; in amdgpu_info_ioctl()
937 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); in amdgpu_info_ioctl()
938 dev_info->pcie_gen = fls(pcie_gen_mask); in amdgpu_info_ioctl()
939 dev_info->pcie_num_lanes = in amdgpu_info_ioctl()
940 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : in amdgpu_info_ioctl()
941 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : in amdgpu_info_ioctl()
942 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : in amdgpu_info_ioctl()
943 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : in amdgpu_info_ioctl()
944 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : in amdgpu_info_ioctl()
945 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; in amdgpu_info_ioctl()
947 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; in amdgpu_info_ioctl()
948 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; in amdgpu_info_ioctl()
949 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; in amdgpu_info_ioctl()
950 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in amdgpu_info_ioctl()
951 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * in amdgpu_info_ioctl()
952 adev->gfx.config.gc_gl1c_per_sa; in amdgpu_info_ioctl()
953 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; in amdgpu_info_ioctl()
954 dev_info->mall_size = adev->gmc.mall_size; in amdgpu_info_ioctl()
957 if (adev->gfx.funcs->get_gfx_shadow_info) { in amdgpu_info_ioctl()
962 dev_info->shadow_size = shadow_info.shadow_size; in amdgpu_info_ioctl()
963 dev_info->shadow_alignment = shadow_info.shadow_alignment; in amdgpu_info_ioctl()
964 dev_info->csa_size = shadow_info.csa_size; in amdgpu_info_ioctl()
965 dev_info->csa_alignment = shadow_info.csa_alignment; in amdgpu_info_ioctl()
970 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; in amdgpu_info_ioctl()
982 vce_clk_table.entries[i].sclk = vce_state->sclk; in amdgpu_info_ioctl()
983 vce_clk_table.entries[i].mclk = vce_state->mclk; in amdgpu_info_ioctl()
984 vce_clk_table.entries[i].eclk = vce_state->evclk; in amdgpu_info_ioctl()
990 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; in amdgpu_info_ioctl()
993 uint32_t bios_size = adev->bios_size; in amdgpu_info_ioctl()
995 switch (info->vbios_info.type) { in amdgpu_info_ioctl()
998 min((size_t)size, sizeof(bios_size))) in amdgpu_info_ioctl()
999 ? -EFAULT : 0; in amdgpu_info_ioctl()
1002 uint32_t bios_offset = info->vbios_info.offset; in amdgpu_info_ioctl()
1005 return -EINVAL; in amdgpu_info_ioctl()
1007 bios = adev->bios + bios_offset; in amdgpu_info_ioctl()
1009 min((size_t)size, (size_t)(bios_size - bios_offset))) in amdgpu_info_ioctl()
1010 ? -EFAULT : 0; in amdgpu_info_ioctl()
1016 atom_context = adev->mode_info.atom_context; in amdgpu_info_ioctl()
1018 memcpy(vbios_info.name, atom_context->name, in amdgpu_info_ioctl()
1019 sizeof(atom_context->name)); in amdgpu_info_ioctl()
1020 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, in amdgpu_info_ioctl()
1021 sizeof(atom_context->vbios_pn)); in amdgpu_info_ioctl()
1022 vbios_info.version = atom_context->version; in amdgpu_info_ioctl()
1023 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, in amdgpu_info_ioctl()
1024 sizeof(atom_context->vbios_ver_str)); in amdgpu_info_ioctl()
1025 memcpy(vbios_info.date, atom_context->date, in amdgpu_info_ioctl()
1026 sizeof(atom_context->date)); in amdgpu_info_ioctl()
1030 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1034 info->vbios_info.type); in amdgpu_info_ioctl()
1035 return -EINVAL; in amdgpu_info_ioctl()
1041 switch (info->query_hw_ip.type) { in amdgpu_info_ioctl()
1044 if (adev->asic_type < CHIP_POLARIS10) { in amdgpu_info_ioctl()
1045 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
1049 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1051 return -ENODATA; in amdgpu_info_ioctl()
1056 return -EINVAL; in amdgpu_info_ioctl()
1060 if (!adev->pm.dpm_enabled) in amdgpu_info_ioctl()
1061 return -ENOENT; in amdgpu_info_ioctl()
1063 switch (info->sensor_info.type) { in amdgpu_info_ioctl()
1069 return -EINVAL; in amdgpu_info_ioctl()
1078 return -EINVAL; in amdgpu_info_ioctl()
1087 return -EINVAL; in amdgpu_info_ioctl()
1095 return -EINVAL; in amdgpu_info_ioctl()
1107 return -EINVAL; in amdgpu_info_ioctl()
1117 return -EINVAL; in amdgpu_info_ioctl()
1126 return -EINVAL; in amdgpu_info_ioctl()
1134 return -EINVAL; in amdgpu_info_ioctl()
1142 return -EINVAL; in amdgpu_info_ioctl()
1151 return -EINVAL; in amdgpu_info_ioctl()
1160 return -EINVAL; in amdgpu_info_ioctl()
1169 return -EINVAL; in amdgpu_info_ioctl()
1175 info->sensor_info.type); in amdgpu_info_ioctl()
1176 return -EINVAL; in amdgpu_info_ioctl()
1178 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
1181 ui32 = atomic_read(&adev->vram_lost_counter); in amdgpu_info_ioctl()
1182 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()
1188 return -EINVAL; in amdgpu_info_ioctl()
1189 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; in amdgpu_info_ioctl()
1193 -EFAULT : 0; in amdgpu_info_ioctl()
1200 if (!adev->asic_funcs->query_video_codecs) in amdgpu_info_ioctl()
1201 return -EINVAL; in amdgpu_info_ioctl()
1203 switch (info->video_cap.type) { in amdgpu_info_ioctl()
1207 return -EINVAL; in amdgpu_info_ioctl()
1212 return -EINVAL; in amdgpu_info_ioctl()
1216 info->video_cap.type); in amdgpu_info_ioctl()
1217 return -EINVAL; in amdgpu_info_ioctl()
1222 return -ENOMEM; in amdgpu_info_ioctl()
1224 for (i = 0; i < codecs->codec_count; i++) { in amdgpu_info_ioctl()
1225 int idx = codecs->codec_array[i].codec_type; in amdgpu_info_ioctl()
1236 caps->codec_info[idx].valid = 1; in amdgpu_info_ioctl()
1237 caps->codec_info[idx].max_width = in amdgpu_info_ioctl()
1238 codecs->codec_array[i].max_width; in amdgpu_info_ioctl()
1239 caps->codec_info[idx].max_height = in amdgpu_info_ioctl()
1240 codecs->codec_array[i].max_height; in amdgpu_info_ioctl()
1241 caps->codec_info[idx].max_pixels_per_frame = in amdgpu_info_ioctl()
1242 codecs->codec_array[i].max_pixels_per_frame; in amdgpu_info_ioctl()
1243 caps->codec_info[idx].max_level = in amdgpu_info_ioctl()
1244 codecs->codec_array[i].max_level; in amdgpu_info_ioctl()
1251 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1262 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1265 struct amdgpu_fpriv *fpriv = filp->driver_priv; in amdgpu_info_ioctl()
1266 struct amdgpu_vm *vm = &fpriv->vm; in amdgpu_info_ioctl()
1271 return -EINVAL; in amdgpu_info_ioctl()
1275 xa_lock_irqsave(&adev->vm_manager.pasids, flags); in amdgpu_info_ioctl()
1276 gpuvm_fault.addr = vm->fault_info.addr; in amdgpu_info_ioctl()
1277 gpuvm_fault.status = vm->fault_info.status; in amdgpu_info_ioctl()
1278 gpuvm_fault.vmhub = vm->fault_info.vmhub; in amdgpu_info_ioctl()
1279 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); in amdgpu_info_ioctl()
1282 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1285 DRM_DEBUG_KMS("Invalid request %d\n", info->query); in amdgpu_info_ioctl()
1286 return -EINVAL; in amdgpu_info_ioctl()
1292 * amdgpu_driver_open_kms - drm callback for open
1307 flush_delayed_work(&adev->delayed_init_work); in amdgpu_driver_open_kms()
1312 return -EHWPOISON; in amdgpu_driver_open_kms()
1315 file_priv->driver_priv = NULL; in amdgpu_driver_open_kms()
1317 r = pm_runtime_get_sync(dev->dev); in amdgpu_driver_open_kms()
1323 r = -ENOMEM; in amdgpu_driver_open_kms()
1329 dev_warn(adev->dev, "No more PASIDs available!"); in amdgpu_driver_open_kms()
1337 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); in amdgpu_driver_open_kms()
1341 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); in amdgpu_driver_open_kms()
1345 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); in amdgpu_driver_open_kms()
1346 if (!fpriv->prt_va) { in amdgpu_driver_open_kms()
1347 r = -ENOMEM; in amdgpu_driver_open_kms()
1351 if (adev->gfx.mcbp) { in amdgpu_driver_open_kms()
1354 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, in amdgpu_driver_open_kms()
1355 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); in amdgpu_driver_open_kms()
1360 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); in amdgpu_driver_open_kms()
1364 mutex_init(&fpriv->bo_list_lock); in amdgpu_driver_open_kms()
1365 idr_init_base(&fpriv->bo_list_handles, 1); in amdgpu_driver_open_kms()
1367 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); in amdgpu_driver_open_kms()
1369 file_priv->driver_priv = fpriv; in amdgpu_driver_open_kms()
1373 amdgpu_vm_fini(adev, &fpriv->vm); in amdgpu_driver_open_kms()
1378 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); in amdgpu_driver_open_kms()
1384 pm_runtime_mark_last_busy(dev->dev); in amdgpu_driver_open_kms()
1386 pm_runtime_put_autosuspend(dev->dev); in amdgpu_driver_open_kms()
1392 * amdgpu_driver_postclose_kms - drm callback for post close
1403 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; in amdgpu_driver_postclose_kms()
1412 pm_runtime_get_sync(dev->dev); in amdgpu_driver_postclose_kms()
1419 if (fpriv->csa_va) { in amdgpu_driver_postclose_kms()
1422 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, in amdgpu_driver_postclose_kms()
1423 fpriv->csa_va, csa_addr)); in amdgpu_driver_postclose_kms()
1424 fpriv->csa_va = NULL; in amdgpu_driver_postclose_kms()
1429 pasid = fpriv->vm.pasid; in amdgpu_driver_postclose_kms()
1430 pd = amdgpu_bo_ref(fpriv->vm.root.bo); in amdgpu_driver_postclose_kms()
1432 amdgpu_vm_bo_del(adev, fpriv->prt_va); in amdgpu_driver_postclose_kms()
1436 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); in amdgpu_driver_postclose_kms()
1437 amdgpu_vm_fini(adev, &fpriv->vm); in amdgpu_driver_postclose_kms()
1440 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); in amdgpu_driver_postclose_kms()
1443 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) in amdgpu_driver_postclose_kms()
1446 idr_destroy(&fpriv->bo_list_handles); in amdgpu_driver_postclose_kms()
1447 mutex_destroy(&fpriv->bo_list_lock); in amdgpu_driver_postclose_kms()
1450 file_priv->driver_priv = NULL; in amdgpu_driver_postclose_kms()
1452 pm_runtime_mark_last_busy(dev->dev); in amdgpu_driver_postclose_kms()
1453 pm_runtime_put_autosuspend(dev->dev); in amdgpu_driver_postclose_kms()
1462 pci_set_drvdata(adev->pdev, NULL); in amdgpu_driver_release_kms()
1469 * amdgpu_get_vblank_counter_kms - get frame count
1474 * Returns frame count on success, -EINVAL on failure.
1478 struct drm_device *dev = crtc->dev; in amdgpu_get_vblank_counter_kms()
1479 unsigned int pipe = crtc->index; in amdgpu_get_vblank_counter_kms()
1484 if (pipe >= adev->mode_info.num_crtc) { in amdgpu_get_vblank_counter_kms()
1486 return -EINVAL; in amdgpu_get_vblank_counter_kms()
1497 if (adev->mode_info.crtcs[pipe]) { in amdgpu_get_vblank_counter_kms()
1510 &adev->mode_info.crtcs[pipe]->base.hwmode); in amdgpu_get_vblank_counter_kms()
1537 * amdgpu_enable_vblank_kms - enable vblank interrupt
1542 * Returns 0 on success, -EINVAL on failure.
1546 struct drm_device *dev = crtc->dev; in amdgpu_enable_vblank_kms()
1547 unsigned int pipe = crtc->index; in amdgpu_enable_vblank_kms()
1551 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); in amdgpu_enable_vblank_kms()
1555 * amdgpu_disable_vblank_kms - disable vblank interrupt
1563 struct drm_device *dev = crtc->dev; in amdgpu_disable_vblank_kms()
1564 unsigned int pipe = crtc->index; in amdgpu_disable_vblank_kms()
1568 amdgpu_irq_put(adev, &adev->crtc_irq, idx); in amdgpu_disable_vblank_kms()
1578 struct amdgpu_device *adev = m->private; in amdgpu_debugfs_firmware_info_show()
1581 struct atom_context *ctx = adev->mode_info.atom_context; in amdgpu_debugfs_firmware_info_show()
1601 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1609 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1617 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1625 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1633 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1641 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1649 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1657 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1665 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1673 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1681 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1689 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1698 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1702 if (adev->gfx.mec2_fw) { in amdgpu_debugfs_firmware_info_show()
1707 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1717 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1725 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1734 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1744 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1757 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", in amdgpu_debugfs_firmware_info_show()
1762 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_debugfs_firmware_info_show()
1767 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1776 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1784 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1792 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1800 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1804 if (adev->psp.cap_fw) { in amdgpu_debugfs_firmware_info_show()
1809 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1818 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1826 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1834 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", in amdgpu_debugfs_firmware_info_show()
1837 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); in amdgpu_debugfs_firmware_info_show()
1849 struct drm_minor *minor = adev_to_drm(adev)->primary; in amdgpu_debugfs_firmware_init()
1850 struct dentry *root = minor->debugfs_root; in amdgpu_debugfs_firmware_init()