359 struct amdgpu_gfx {  struct
361 	struct amdgpu_gfx_config	config;  argument
362 	struct amdgpu_rlc		rlc;
363 	struct amdgpu_pfp		pfp;
364 	struct amdgpu_ce		ce;
365 	struct amdgpu_me		me;
366 	struct amdgpu_mec		mec;
367 	struct amdgpu_mec_bitmap	mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
368 	struct amdgpu_kiq		kiq[AMDGPU_MAX_GC_INSTANCES];
369 	struct amdgpu_imu		imu;
370 	bool				rs64_enable; /* firmware format */
371 	const struct firmware		*me_fw;	/* ME firmware */
372 	uint32_t			me_fw_version;
373 	const struct firmware		*pfp_fw; /* PFP firmware */
374 	uint32_t			pfp_fw_version;
375 	const struct firmware		*ce_fw;	/* CE firmware */
376 	uint32_t			ce_fw_version;
377 	const struct firmware		*rlc_fw; /* RLC firmware */
378 	uint32_t			rlc_fw_version;
379 	const struct firmware		*mec_fw; /* MEC firmware */
380 	uint32_t			mec_fw_version;
381 	const struct firmware		*mec2_fw; /* MEC2 firmware */
382 	uint32_t			mec2_fw_version;
383 	const struct firmware		*imu_fw; /* IMU firmware */
384 	uint32_t			imu_fw_version;
385 	uint32_t			me_feature_version;
386 	uint32_t			ce_feature_version;
387 	uint32_t			pfp_feature_version;
388 	uint32_t			rlc_feature_version;
389 	uint32_t			rlc_srlc_fw_version;
390 	uint32_t			rlc_srlc_feature_version;
391 	uint32_t			rlc_srlg_fw_version;
392 	uint32_t			rlc_srlg_feature_version;
393 	uint32_t			rlc_srls_fw_version;
394 	uint32_t			rlc_srls_feature_version;
395 	uint32_t			rlcp_ucode_version;
396 	uint32_t			rlcp_ucode_feature_version;
397 	uint32_t			rlcv_ucode_version;
398 	uint32_t			rlcv_ucode_feature_version;
422 	const struct amdgpu_gfx_funcs	*funcs;  argument
442 	struct amdgpu_gfx_ras		*ras;  argument
444 	bool				is_poweron;
446 	struct amdgpu_ring		sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
447 	struct amdgpu_ring_mux          muxer;
449 	bool				cp_gfx_shadow; /* for gfx11 */
451 	uint16_t 			xcc_mask;
452 	uint32_t			num_xcc_per_xcp;
453 	struct mutex			partition_mutex;
477 struct amdgpu_gfx_ras_reg_entry {  argument