51 #include <linux/dma-fence.h>
312 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
431 /* sub-allocation manager, it has to be protected by another lock.
441  * the end total_size - (last_object_offset + last_object_size) >=
506 #define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
510 	volatile uint32_t	*wb;  member
512 	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
517 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
518 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
534  * enum amd_reset_method - Methods for resetting AMD GPU devices
559 	AMD_RESET_METHOD_NONE = -1,
830  * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
832 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
933 	struct amdgpu_wb		wb;  member
953 	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
1046 	/* isp */
1047 	struct amdgpu_isp		isp;  member
1177 	return adev->ip_versions[ip][inst] & ~0xFFU;  in amdgpu_ip_version()
1183 	/* This returns full version - major/minor/rev/variant/subrevision */  in amdgpu_ip_version_full()
1184 	return adev->ip_versions[ip][inst];  in amdgpu_ip_version_full()
1194 	return &adev->ddev;  in adev_to_drm()
1288 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1289 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1290 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1291 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1292 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1293 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1294 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1295 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1296 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1297 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1298 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1299 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1300 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1301 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1302 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1303 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1304 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1305 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1306 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1307 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1308 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1309 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1357 #define RBIOS8(i) (adev->bios[i])
1365     ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1366 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1367 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1368 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1369 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1370 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (…
1371 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1372 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1373 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1374 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1375 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (…
1376 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev)…
1377 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1379 …((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->f…
1381 	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1382 	 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1383 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1384 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1385 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (c…
1386 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1387 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1388 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1389 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1391 …((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev…
1392 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (…
1394 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1398 	for (i = ffs(inst_mask); i-- != 0; \
1551 	return -EINVAL;  in amdgpu_acpi_get_tmr_info()
1557 	return -EINVAL;  in amdgpu_acpi_get_mem_info()
1603 		adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&  in amdgpu_device_has_timeouts_enabled()
1604 		adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&  in amdgpu_device_has_timeouts_enabled()
1605 		adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&  in amdgpu_device_has_timeouts_enabled()
1606 		adev->video_timeout != MAX_SCHEDULE_TIMEOUT;  in amdgpu_device_has_timeouts_enabled()
1613        return adev->gmc.tmz_enabled;  in amdgpu_is_tmz()