Lines Matching +full:needs +full:- +full:reset +full:- +full:on +full:- +full:resume
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in aldebaran_is_mode2_default()
39 adev->gmc.xgmi.connected_to_cpu)) in aldebaran_is_mode2_default()
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in aldebaran_get_reset_handler()
53 if (reset_context->method == AMD_RESET_METHOD_NONE) { in aldebaran_get_reset_handler()
55 reset_context->method = AMD_RESET_METHOD_MODE2; in aldebaran_get_reset_handler()
57 reset_context->method = amdgpu_asic_reset_method(adev); in aldebaran_get_reset_handler()
60 if (reset_context->method != AMD_RESET_METHOD_NONE) { in aldebaran_get_reset_handler()
61 dev_dbg(adev->dev, "Getting reset handler for method %d\n", in aldebaran_get_reset_handler()
62 reset_context->method); in aldebaran_get_reset_handler()
64 if (handler->reset_method == reset_context->method) in aldebaran_get_reset_handler()
69 dev_dbg(adev->dev, "Reset handler not found!\n"); in aldebaran_get_reset_handler()
81 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { in aldebaran_mode2_suspend_ip()
82 if (!(adev->ip_blocks[i].version->type == in aldebaran_mode2_suspend_ip()
84 adev->ip_blocks[i].version->type == in aldebaran_mode2_suspend_ip()
88 r = adev->ip_blocks[i].version->funcs->suspend(adev); in aldebaran_mode2_suspend_ip()
91 dev_err(adev->dev, in aldebaran_mode2_suspend_ip()
93 adev->ip_blocks[i].version->funcs->name, r); in aldebaran_mode2_suspend_ip()
97 adev->ip_blocks[i].status.hw = false; in aldebaran_mode2_suspend_ip()
108 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in aldebaran_mode2_prepare_hwcontext()
110 dev_dbg(adev->dev, "Aldebaran prepare hw context\n"); in aldebaran_mode2_prepare_hwcontext()
111 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ in aldebaran_mode2_prepare_hwcontext()
123 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in aldebaran_async_reset()
127 if (handler->reset_method == reset_ctl->active_reset) { in aldebaran_async_reset()
128 dev_dbg(adev->dev, "Resetting device\n"); in aldebaran_async_reset()
129 handler->do_reset(adev); in aldebaran_async_reset()
138 pci_clear_master(adev->pdev); in aldebaran_mode2_reset()
139 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev); in aldebaran_mode2_reset()
140 return adev->asic_reset_res; in aldebaran_mode2_reset()
147 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; in aldebaran_mode2_perform_reset()
148 struct list_head *reset_device_list = reset_context->reset_device_list; in aldebaran_mode2_perform_reset()
152 dev_dbg(adev->dev, "aldebaran perform hw reset\n"); in aldebaran_mode2_perform_reset()
155 return -EINVAL; in aldebaran_mode2_perform_reset()
158 reset_context->hive == NULL) { in aldebaran_mode2_perform_reset()
160 return -EINVAL; in aldebaran_mode2_perform_reset()
164 mutex_lock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
165 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; in aldebaran_mode2_perform_reset()
168 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch in aldebaran_mode2_perform_reset()
169 * them together so that they can be completed asynchronously on multiple nodes in aldebaran_mode2_perform_reset()
173 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { in aldebaran_mode2_perform_reset()
175 &tmp_adev->reset_cntl->reset_work)) in aldebaran_mode2_perform_reset()
176 r = -EALREADY; in aldebaran_mode2_perform_reset()
180 dev_err(tmp_adev->dev, in aldebaran_mode2_perform_reset()
181 "ASIC reset failed with error, %d for drm dev, %s", in aldebaran_mode2_perform_reset()
182 r, adev_to_drm(tmp_adev)->unique); in aldebaran_mode2_perform_reset()
190 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { in aldebaran_mode2_perform_reset()
191 flush_work(&tmp_adev->reset_cntl->reset_work); in aldebaran_mode2_perform_reset()
192 r = tmp_adev->asic_reset_res; in aldebaran_mode2_perform_reset()
200 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
201 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; in aldebaran_mode2_perform_reset()
215 dev_dbg(adev->dev, "Reloading ucodes after reset\n"); in aldebaran_mode2_restore_ip()
216 for (i = 0; i < adev->firmware.max_ucodes; i++) { in aldebaran_mode2_restore_ip()
217 ucode = &adev->firmware.ucode[i]; in aldebaran_mode2_restore_ip()
218 if (!ucode->fw) in aldebaran_mode2_restore_ip()
220 switch (ucode->ucode_id) { in aldebaran_mode2_restore_ip()
246 dev_err(adev->dev, "Failed to get BIF handle\n"); in aldebaran_mode2_restore_ip()
247 return -EINVAL; in aldebaran_mode2_restore_ip()
249 r = cmn_block->version->funcs->resume(adev); in aldebaran_mode2_restore_ip()
254 adev->gfxhub.funcs->init(adev); in aldebaran_mode2_restore_ip()
255 r = adev->gfxhub.funcs->gart_enable(adev); in aldebaran_mode2_restore_ip()
257 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n"); in aldebaran_mode2_restore_ip()
262 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count); in aldebaran_mode2_restore_ip()
264 dev_err(adev->dev, "GFX ucode load failed after reset\n"); in aldebaran_mode2_restore_ip()
268 /* Resume RLC, FW needs RLC alive to complete reset process */ in aldebaran_mode2_restore_ip()
269 adev->gfx.rlc.funcs->resume(adev); in aldebaran_mode2_restore_ip()
271 /* Wait for FW reset event complete */ in aldebaran_mode2_restore_ip()
274 dev_err(adev->dev, in aldebaran_mode2_restore_ip()
275 "Failed to get response from firmware after reset\n"); in aldebaran_mode2_restore_ip()
279 for (i = 0; i < adev->num_ip_blocks; i++) { in aldebaran_mode2_restore_ip()
280 if (!(adev->ip_blocks[i].version->type == in aldebaran_mode2_restore_ip()
282 adev->ip_blocks[i].version->type == in aldebaran_mode2_restore_ip()
285 r = adev->ip_blocks[i].version->funcs->resume(adev); in aldebaran_mode2_restore_ip()
287 dev_err(adev->dev, in aldebaran_mode2_restore_ip()
288 "resume of IP block <%s> failed %d\n", in aldebaran_mode2_restore_ip()
289 adev->ip_blocks[i].version->funcs->name, r); in aldebaran_mode2_restore_ip()
293 adev->ip_blocks[i].status.hw = true; in aldebaran_mode2_restore_ip()
296 for (i = 0; i < adev->num_ip_blocks; i++) { in aldebaran_mode2_restore_ip()
297 if (!(adev->ip_blocks[i].version->type == in aldebaran_mode2_restore_ip()
299 adev->ip_blocks[i].version->type == in aldebaran_mode2_restore_ip()
301 adev->ip_blocks[i].version->type == in aldebaran_mode2_restore_ip()
305 if (adev->ip_blocks[i].version->funcs->late_init) { in aldebaran_mode2_restore_ip()
306 r = adev->ip_blocks[i].version->funcs->late_init( in aldebaran_mode2_restore_ip()
309 dev_err(adev->dev, in aldebaran_mode2_restore_ip()
310 "late_init of IP block <%s> failed %d after reset\n", in aldebaran_mode2_restore_ip()
311 adev->ip_blocks[i].version->funcs->name, in aldebaran_mode2_restore_ip()
316 adev->ip_blocks[i].status.late_initialized = true; in aldebaran_mode2_restore_ip()
329 struct list_head *reset_device_list = reset_context->reset_device_list; in aldebaran_mode2_restore_hwcontext()
335 return -EINVAL; in aldebaran_mode2_restore_hwcontext()
337 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) == in aldebaran_mode2_restore_hwcontext()
339 reset_context->hive == NULL) { in aldebaran_mode2_restore_hwcontext()
341 return -EINVAL; in aldebaran_mode2_restore_hwcontext()
345 dev_info(tmp_adev->dev, in aldebaran_mode2_restore_hwcontext()
346 "GPU reset succeeded, trying to resume\n"); in aldebaran_mode2_restore_hwcontext()
352 * Add this ASIC as tracked as reset was already in aldebaran_mode2_restore_hwcontext()
357 /* Resume RAS, ecc_irq */ in aldebaran_mode2_restore_hwcontext()
360 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
361 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
362 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
363 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
365 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r); in aldebaran_mode2_restore_hwcontext()
370 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
371 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
372 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
373 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
375 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r); in aldebaran_mode2_restore_hwcontext()
383 /* Update PSP FW topology after reset */ in aldebaran_mode2_restore_hwcontext()
384 if (reset_context->hive && in aldebaran_mode2_restore_hwcontext()
385 tmp_adev->gmc.xgmi.num_physical_nodes > 1) in aldebaran_mode2_restore_hwcontext()
386 r = amdgpu_xgmi_update_topology(reset_context->hive, in aldebaran_mode2_restore_hwcontext()
394 dev_err(tmp_adev->dev, in aldebaran_mode2_restore_hwcontext()
396 r = -EAGAIN; in aldebaran_mode2_restore_hwcontext()
397 tmp_adev->asic_reset_res = r; in aldebaran_mode2_restore_hwcontext()
428 return -ENOMEM; in aldebaran_reset_init()
430 reset_ctl->handle = adev; in aldebaran_reset_init()
431 reset_ctl->async_reset = aldebaran_async_reset; in aldebaran_reset_init()
432 reset_ctl->active_reset = AMD_RESET_METHOD_NONE; in aldebaran_reset_init()
433 reset_ctl->get_reset_handler = aldebaran_get_reset_handler; in aldebaran_reset_init()
435 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); in aldebaran_reset_init()
436 /* Only mode2 is handled through reset control now */ in aldebaran_reset_init()
437 reset_ctl->reset_handlers = &aldebaran_rst_handlers; in aldebaran_reset_init()
439 adev->reset_cntl = reset_ctl; in aldebaran_reset_init()
446 kfree(adev->reset_cntl); in aldebaran_reset_fini()
447 adev->reset_cntl = NULL; in aldebaran_reset_fini()