drivers/gpio/gpio-ws16c48.c

1 // SPDX-License-Identifier: GPL-2.0-only
42 #define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
89 /* Only the first 24 lines (Port 0-2) support interrupts */
92 	WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
93 	WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
94 	WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
95 	WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
96 	WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
97 	WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
98 	WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
99 	WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
103  * struct ws16c48_gpio - GPIO device private data structure
114 static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)  in ws16c48_handle_pre_irq()
119 	raw_spin_lock(&ws16c48gpio->lock);  in ws16c48_handle_pre_irq()
124 static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)  in ws16c48_handle_post_irq()
128 	raw_spin_unlock(&ws16c48gpio->lock);  in ws16c48_handle_post_irq()
140 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);  in ws16c48_handle_mask_sync()
143 	if (mask_buf == ws16c48gpio->irq_mask[index])  in ws16c48_handle_mask_sync()
145 	ws16c48gpio->irq_mask[index] = mask_buf;  in ws16c48_handle_mask_sync()
147 	ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);  in ws16c48_handle_mask_sync()
152 	ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);  in ws16c48_handle_mask_sync()
156 	ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);  in ws16c48_handle_mask_sync()
161 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);  in ws16c48_handle_mask_sync()
177 		polarity = irq_data->mask;  in ws16c48_set_type_config()
183 		return -EINVAL;  in ws16c48_set_type_config()
186 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);  in ws16c48_set_type_config()
188 	ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);  in ws16c48_set_type_config()
193 	ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);  in ws16c48_set_type_config()
197 	ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);  in ws16c48_set_type_config()
202 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);  in ws16c48_set_type_config()
209 	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
210 	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
211 	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
212 	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
213 	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
214 	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
215 	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
216 	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
217 	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
218 	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
219 	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
220 	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
238 	err = regmap_write(map, WS16C48_ENAB + 2, 0x00);  in ws16c48_irq_init_hw()
257 		return -ENOMEM;  in ws16c48_probe()
260 		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",  in ws16c48_probe()
262 		return -EBUSY;  in ws16c48_probe()
267 		return -ENOMEM;  in ws16c48_probe()
269 	ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);  in ws16c48_probe()
270 	if (IS_ERR(ws16c48gpio->map))  in ws16c48_probe()
271 		return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),  in ws16c48_probe()
276 		return -ENOMEM;  in ws16c48_probe()
278 	chip->name = name;  in ws16c48_probe()
279 	chip->status_base = WS16C48_INT_ID;  in ws16c48_probe()
280 	chip->mask_base = WS16C48_ENAB;  in ws16c48_probe()
281 	chip->ack_base = WS16C48_INT_ID;  in ws16c48_probe()
282 	chip->num_regs = 3;  in ws16c48_probe()
283 	chip->irqs = ws16c48_regmap_irqs;  in ws16c48_probe()
284 	chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);  in ws16c48_probe()
285 	chip->handle_pre_irq = ws16c48_handle_pre_irq;  in ws16c48_probe()
286 	chip->handle_post_irq = ws16c48_handle_post_irq;  in ws16c48_probe()
287 	chip->handle_mask_sync = ws16c48_handle_mask_sync;  in ws16c48_probe()
288 	chip->set_type_config = ws16c48_set_type_config;  in ws16c48_probe()
289 	chip->irq_drv_data = ws16c48gpio;  in ws16c48_probe()
291 	raw_spin_lock_init(&ws16c48gpio->lock);  in ws16c48_probe()
294 	err = ws16c48_irq_init_hw(ws16c48gpio->map);  in ws16c48_probe()
298 	err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);  in ws16c48_probe()
303 	gpio_config.regmap = ws16c48gpio->map;  in ws16c48_probe()