1 // SPDX-License-Identifier: GPL-2.0-only
21 #define DRIVER_NAME "timb-gpio"
36 	spinlock_t		lock; /* mutual exclusion */  member
43 	unsigned offset, bool enabled)  in timbgpio_update_bit()  argument
49 	spin_lock_irqsave(&tgpio->lock, flags);  in timbgpio_update_bit()
50 	reg = ioread32(tgpio->membase + offset);  in timbgpio_update_bit()
57 	iowrite32(reg, tgpio->membase + offset);  in timbgpio_update_bit()
58 	spin_unlock_irqrestore(&tgpio->lock, flags);  in timbgpio_update_bit()
73 	value = ioread32(tgpio->membase + TGPIOVAL);  in timbgpio_gpio_get()
89 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)  in timbgpio_to_irq()  argument
93 	if (tgpio->irq_base <= 0)  in timbgpio_to_irq()
94 		return -EINVAL;  in timbgpio_to_irq()
96 	return tgpio->irq_base + offset;  in timbgpio_to_irq()
105 	int offset = d->irq - tgpio->irq_base;  in timbgpio_irq_disable()  local
108 	spin_lock_irqsave(&tgpio->lock, flags);  in timbgpio_irq_disable()
109 	tgpio->last_ier &= ~(1UL << offset);  in timbgpio_irq_disable()
110 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);  in timbgpio_irq_disable()
111 	spin_unlock_irqrestore(&tgpio->lock, flags);  in timbgpio_irq_disable()
117 	int offset = d->irq - tgpio->irq_base;  in timbgpio_irq_enable()  local
120 	spin_lock_irqsave(&tgpio->lock, flags);  in timbgpio_irq_enable()
121 	tgpio->last_ier |= 1UL << offset;  in timbgpio_irq_enable()
122 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);  in timbgpio_irq_enable()
123 	spin_unlock_irqrestore(&tgpio->lock, flags);  in timbgpio_irq_enable()
129 	int offset = d->irq - tgpio->irq_base;  in timbgpio_irq_type()  local
135 	if (offset < 0 || offset > tgpio->gpio.ngpio)  in timbgpio_irq_type()
136 		return -EINVAL;  in timbgpio_irq_type()
138 	ver = ioread32(tgpio->membase + TGPIO_VER);  in timbgpio_irq_type()
140 	spin_lock_irqsave(&tgpio->lock, flags);  in timbgpio_irq_type()
142 	lvr = ioread32(tgpio->membase + TGPIO_LVR);  in timbgpio_irq_type()
143 	flr = ioread32(tgpio->membase + TGPIO_FLR);  in timbgpio_irq_type()
145 		bflr = ioread32(tgpio->membase + TGPIO_BFLR);  in timbgpio_irq_type()
148 		bflr &= ~(1 << offset);  in timbgpio_irq_type()
149 		flr &= ~(1 << offset);  in timbgpio_irq_type()
151 			lvr |= 1 << offset;  in timbgpio_irq_type()
153 			lvr &= ~(1 << offset);  in timbgpio_irq_type()
158 			ret = -EINVAL;  in timbgpio_irq_type()
161 			flr |= 1 << offset;  in timbgpio_irq_type()
162 			bflr |= 1 << offset;  in timbgpio_irq_type()
165 		bflr &= ~(1 << offset);  in timbgpio_irq_type()
166 		flr |= 1 << offset;  in timbgpio_irq_type()
168 			lvr &= ~(1 << offset);  in timbgpio_irq_type()
170 			lvr |= 1 << offset;  in timbgpio_irq_type()
173 	iowrite32(lvr, tgpio->membase + TGPIO_LVR);  in timbgpio_irq_type()
174 	iowrite32(flr, tgpio->membase + TGPIO_FLR);  in timbgpio_irq_type()
176 		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);  in timbgpio_irq_type()
178 	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);  in timbgpio_irq_type()
181 	spin_unlock_irqrestore(&tgpio->lock, flags);  in timbgpio_irq_type()
190 	int offset;  in timbgpio_irq()  local
192 	data->chip->irq_ack(data);  in timbgpio_irq()
193 	ipr = ioread32(tgpio->membase + TGPIO_IPR);  in timbgpio_irq()
194 	iowrite32(ipr, tgpio->membase + TGPIO_ICR);  in timbgpio_irq()
200 	iowrite32(0, tgpio->membase + TGPIO_IER);  in timbgpio_irq()
202 	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)  in timbgpio_irq()
203 		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));  in timbgpio_irq()
205 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);  in timbgpio_irq()
218 	struct device *dev = &pdev->dev;  in timbgpio_probe()
221 	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);  in timbgpio_probe()
224 	if (!pdata || pdata->nr_pins > 32) {  in timbgpio_probe()
226 		return -EINVAL;  in timbgpio_probe()
231 		return -EINVAL;  in timbgpio_probe()
233 	tgpio->irq_base = pdata->irq_base;  in timbgpio_probe()
235 	spin_lock_init(&tgpio->lock);  in timbgpio_probe()
237 	tgpio->membase = devm_platform_ioremap_resource(pdev, 0);  in timbgpio_probe()
238 	if (IS_ERR(tgpio->membase))  in timbgpio_probe()
239 		return PTR_ERR(tgpio->membase);  in timbgpio_probe()
241 	gc = &tgpio->gpio;  in timbgpio_probe()
243 	gc->label = dev_name(&pdev->dev);  in timbgpio_probe()
244 	gc->owner = THIS_MODULE;  in timbgpio_probe()
245 	gc->parent = &pdev->dev;  in timbgpio_probe()
246 	gc->direction_input = timbgpio_gpio_direction_input;  in timbgpio_probe()
247 	gc->get = timbgpio_gpio_get;  in timbgpio_probe()
248 	gc->direction_output = timbgpio_gpio_direction_output;  in timbgpio_probe()
249 	gc->set = timbgpio_gpio_set;  in timbgpio_probe()
250 	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;  in timbgpio_probe()
251 	gc->dbg_show = NULL;  in timbgpio_probe()
252 	gc->base = pdata->gpio_base;  in timbgpio_probe()
253 	gc->ngpio = pdata->nr_pins;  in timbgpio_probe()
254 	gc->can_sleep = false;  in timbgpio_probe()
256 	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);  in timbgpio_probe()
261 	iowrite32(0x0, tgpio->membase + TGPIO_IER);  in timbgpio_probe()
263 	if (irq < 0 || tgpio->irq_base <= 0)  in timbgpio_probe()
266 	for (i = 0; i < pdata->nr_pins; i++) {  in timbgpio_probe()
267 		irq_set_chip_and_handler(tgpio->irq_base + i,  in timbgpio_probe()
269 		irq_set_chip_data(tgpio->irq_base + i, tgpio);  in timbgpio_probe()
270 		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);  in timbgpio_probe()
286 /*--------------------------------------------------------------------------*/