Lines Matching +full:hardware +full:- +full:controlled
1 // SPDX-License-Identifier: GPL-2.0-only
22 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
37 /* software or hardware update select bit */
85 u8 groups; /* we can drive 1-3 groups of 8bit each */
95 * xway_stp_get() - gpio_chip->get - get gpios.
105 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); in xway_stp_get()
109 * xway_stp_set() - gpio_chip->set - set gpios.
121 chip->shadow |= BIT(gpio); in xway_stp_set()
123 chip->shadow &= ~BIT(gpio); in xway_stp_set()
124 xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0); in xway_stp_set()
125 if (!chip->reserved) in xway_stp_set()
126 xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0); in xway_stp_set()
130 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
145 * xway_stp_request() - gpio_chip->request
155 if ((gpio < 8) && (chip->reserved & BIT(gpio))) { in xway_stp_request()
156 dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio); in xway_stp_request()
157 return -ENODEV; in xway_stp_request()
164 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
170 xway_stp_w32(chip->virt, 0, XWAY_STP_AR); in xway_stp_hw_init()
171 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0); in xway_stp_hw_init()
172 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1); in xway_stp_hw_init()
173 xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0); in xway_stp_hw_init()
174 xway_stp_w32(chip->virt, 0, XWAY_STP_CON1); in xway_stp_hw_init()
177 xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK, in xway_stp_hw_init()
178 chip->edge, XWAY_STP_CON0); in xway_stp_hw_init()
181 xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK, in xway_stp_hw_init()
182 chip->groups, XWAY_STP_CON1); in xway_stp_hw_init()
184 /* tell the hardware which pins are controlled by the dsl modem */ in xway_stp_hw_init()
185 xway_stp_w32_mask(chip->virt, in xway_stp_hw_init()
187 chip->dsl << XWAY_STP_ADSL_SHIFT, in xway_stp_hw_init()
190 /* tell the hardware which pins are controlled by the phys */ in xway_stp_hw_init()
191 xway_stp_w32_mask(chip->virt, in xway_stp_hw_init()
193 chip->phy1 << XWAY_STP_PHY1_SHIFT, in xway_stp_hw_init()
195 xway_stp_w32_mask(chip->virt, in xway_stp_hw_init()
197 chip->phy2 << XWAY_STP_PHY2_SHIFT, in xway_stp_hw_init()
202 xway_stp_w32_mask(chip->virt, in xway_stp_hw_init()
204 chip->phy3 << XWAY_STP_PHY3_SHIFT, in xway_stp_hw_init()
209 xway_stp_w32_mask(chip->virt, in xway_stp_hw_init()
211 chip->phy4 << XWAY_STP_PHY4_SHIFT, in xway_stp_hw_init()
216 chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5) in xway_stp_hw_init()
217 | (chip->phy1 << 2) | chip->dsl; in xway_stp_hw_init()
223 if (chip->reserved) { in xway_stp_hw_init()
224 xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK, in xway_stp_hw_init()
226 xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK, in xway_stp_hw_init()
228 xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK, in xway_stp_hw_init()
240 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); in xway_stp_probe()
242 return -ENOMEM; in xway_stp_probe()
244 chip->virt = devm_platform_ioremap_resource(pdev, 0); in xway_stp_probe()
245 if (IS_ERR(chip->virt)) in xway_stp_probe()
246 return PTR_ERR(chip->virt); in xway_stp_probe()
248 chip->gc.parent = &pdev->dev; in xway_stp_probe()
249 chip->gc.label = "stp-xway"; in xway_stp_probe()
250 chip->gc.direction_output = xway_stp_dir_out; in xway_stp_probe()
251 chip->gc.get = xway_stp_get; in xway_stp_probe()
252 chip->gc.set = xway_stp_set; in xway_stp_probe()
253 chip->gc.request = xway_stp_request; in xway_stp_probe()
254 chip->gc.base = -1; in xway_stp_probe()
255 chip->gc.owner = THIS_MODULE; in xway_stp_probe()
258 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow)) in xway_stp_probe()
259 chip->shadow = shadow; in xway_stp_probe()
262 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups)) in xway_stp_probe()
263 chip->groups = groups & XWAY_STP_GROUP_MASK; in xway_stp_probe()
265 chip->groups = XWAY_STP_GROUP0; in xway_stp_probe()
266 chip->gc.ngpio = fls(chip->groups) * 8; in xway_stp_probe()
268 /* find out which gpios are controlled by the dsl core */ in xway_stp_probe()
269 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl)) in xway_stp_probe()
270 chip->dsl = dsl & XWAY_STP_ADSL_MASK; in xway_stp_probe()
272 /* find out which gpios are controlled by the phys */ in xway_stp_probe()
278 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy)) in xway_stp_probe()
279 chip->phy1 = phy & XWAY_STP_PHY_MASK; in xway_stp_probe()
280 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy)) in xway_stp_probe()
281 chip->phy2 = phy & XWAY_STP_PHY_MASK; in xway_stp_probe()
286 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy)) in xway_stp_probe()
287 chip->phy3 = phy & XWAY_STP_PHY_MASK; in xway_stp_probe()
291 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy)) in xway_stp_probe()
292 chip->phy4 = phy & XWAY_STP_PHY_MASK; in xway_stp_probe()
296 if (!of_property_read_bool(pdev->dev.of_node, "lantiq,rising")) in xway_stp_probe()
297 chip->edge = XWAY_STP_FALLING; in xway_stp_probe()
299 clk = devm_clk_get_enabled(&pdev->dev, NULL); in xway_stp_probe()
301 dev_err(&pdev->dev, "Failed to get clock\n"); in xway_stp_probe()
307 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); in xway_stp_probe()
311 dev_info(&pdev->dev, "Init done\n"); in xway_stp_probe()
317 { .compatible = "lantiq,gpio-stp-xway" },
325 .name = "gpio-stp-xway",