1 // SPDX-License-Identifier: GPL-2.0-only
3  * linux/arch/arm/mach-sa1100/gpio.c
5  * Generic SA-1100 GPIO handling
40 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)  in sa1100_gpio_get()  argument
42 	return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &  in sa1100_gpio_get()
43 		BIT(offset);  in sa1100_gpio_get()
46 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)  in sa1100_gpio_set()  argument
50 	writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);  in sa1100_gpio_set()
53 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)  in sa1100_get_direction()  argument
55 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;  in sa1100_get_direction()
57 	if (readl_relaxed(gpdr) & BIT(offset))  in sa1100_get_direction()
63 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)  in sa1100_direction_input()  argument
65 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;  in sa1100_direction_input()
69 	writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);  in sa1100_direction_input()
75 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)  in sa1100_direction_output()  argument
77 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;  in sa1100_direction_output()
81 	sa1100_gpio_set(chip, offset, value);  in sa1100_direction_output()
82 	writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);  in sa1100_direction_output()
88 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)  in sa1100_to_irq()  argument
90 	return sa1100_gpio_chip(chip)->irqbase + offset;  in sa1100_to_irq()
110  * SA1100 GPIO edge detection for IRQs:
111  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
116 	void *base = sgc->membase;  in sa1100_update_edge_regs()
119 	grer = sgc->irqrising & sgc->irqmask;  in sa1100_update_edge_regs()
120 	gfer = sgc->irqfalling & sgc->irqmask;  in sa1100_update_edge_regs()
129 	unsigned int mask = BIT(d->hwirq);  in sa1100_gpio_type()
132 		if ((sgc->irqrising | sgc->irqfalling) & mask)  in sa1100_gpio_type()
138 		sgc->irqrising |= mask;  in sa1100_gpio_type()
140 		sgc->irqrising &= ~mask;  in sa1100_gpio_type()
142 		sgc->irqfalling |= mask;  in sa1100_gpio_type()
144 		sgc->irqfalling &= ~mask;  in sa1100_gpio_type()
158 	writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);  in sa1100_gpio_ack()
164 	unsigned int mask = BIT(d->hwirq);  in sa1100_gpio_mask()
166 	sgc->irqmask &= ~mask;  in sa1100_gpio_mask()
174 	unsigned int mask = BIT(d->hwirq);  in sa1100_gpio_unmask()
176 	sgc->irqmask |= mask;  in sa1100_gpio_unmask()
184 	int ret = sa11x0_gpio_set_wake(d->hwirq, on);  in sa1100_gpio_wake()
187 			sgc->irqwake |= BIT(d->hwirq);  in sa1100_gpio_wake()
189 			sgc->irqwake &= ~BIT(d->hwirq);  in sa1100_gpio_wake()
209 	struct sa1100_gpio_chip *sgc = d->host_data;  in sa1100_gpio_irqdomain_map()
226  * IRQ 0-11 (GPIO) handler.  We enter here with the
234 	void __iomem *gedr = sgc->membase + R_GEDR;  in sa1100_gpio_handler()
244 		irq = sgc->irqbase;  in sa1100_gpio_handler()
263 	writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);  in sa1100_gpio_suspend()
264 	writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);  in sa1100_gpio_suspend()
269 	writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),  in sa1100_gpio_suspend()
270 		       sgc->membase + R_GEDR);  in sa1100_gpio_suspend()
294 	/* Install handlers for GPIO 0-10 edge detect interrupts */
306 	/* Install handler for GPIO 11-27 edge detect interrupts */
315 	/* clear all GPIO edge detects */  in sa1100_init_gpio()
316 	writel_relaxed(0, sgc->membase + R_GFER);  in sa1100_init_gpio()
317 	writel_relaxed(0, sgc->membase + R_GRER);  in sa1100_init_gpio()
318 	writel_relaxed(-1, sgc->membase + R_GEDR);  in sa1100_init_gpio()