Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
95 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_output()
96 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
97 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_output()
98 gpiodir |= BIT(offset); in pl061_direction_output()
99 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_output()
105 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
106 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_output()
111 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) in pl061_get_value() argument
115 return !!readb(pl061->base + (BIT(offset + 2))); in pl061_get_value()
118 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) in pl061_set_value() argument
122 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_set_value()
129 int offset = irqd_to_hwirq(d); in pl061_irq_type() local
132 u8 bit = BIT(offset); in pl061_irq_type()
134 if (offset < 0 || offset >= PL061_GPIO_NR) in pl061_irq_type()
135 return -EINVAL; in pl061_irq_type()
140 dev_err(gc->parent, in pl061_irq_type()
141 "trying to configure line %d for both level and edge " in pl061_irq_type()
143 offset); in pl061_irq_type()
144 return -EINVAL; in pl061_irq_type()
148 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_irq_type()
150 gpioiev = readb(pl061->base + GPIOIEV); in pl061_irq_type()
151 gpiois = readb(pl061->base + GPIOIS); in pl061_irq_type()
152 gpioibe = readb(pl061->base + GPIOIBE); in pl061_irq_type()
157 /* Disable edge detection */ in pl061_irq_type()
167 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", in pl061_irq_type()
168 offset, in pl061_irq_type()
176 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); in pl061_irq_type()
185 /* Select edge */ in pl061_irq_type()
191 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", in pl061_irq_type()
192 offset, in pl061_irq_type()
200 dev_warn(gc->parent, "no trigger selected for line %d\n", in pl061_irq_type()
201 offset); in pl061_irq_type()
204 writeb(gpiois, pl061->base + GPIOIS); in pl061_irq_type()
205 writeb(gpioibe, pl061->base + GPIOIBE); in pl061_irq_type()
206 writeb(gpioiev, pl061->base + GPIOIEV); in pl061_irq_type()
208 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_irq_type()
216 int offset; in pl061_irq_handler() local
223 pending = readb(pl061->base + GPIOMIS); in pl061_irq_handler()
225 for_each_set_bit(offset, &pending, PL061_GPIO_NR) in pl061_irq_handler()
226 generic_handle_domain_irq(gc->irq.domain, in pl061_irq_handler()
227 offset); in pl061_irq_handler()
240 raw_spin_lock(&pl061->lock); in pl061_irq_mask()
241 gpioie = readb(pl061->base + GPIOIE) & ~mask; in pl061_irq_mask()
242 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_mask()
243 raw_spin_unlock(&pl061->lock); in pl061_irq_mask()
245 gpiochip_disable_irq(gc, d->hwirq); in pl061_irq_mask()
255 gpiochip_enable_irq(gc, d->hwirq); in pl061_irq_unmask()
257 raw_spin_lock(&pl061->lock); in pl061_irq_unmask()
258 gpioie = readb(pl061->base + GPIOIE) | mask; in pl061_irq_unmask()
259 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_unmask()
260 raw_spin_unlock(&pl061->lock); in pl061_irq_unmask()
264 * pl061_irq_ack() - ACK an edge IRQ
267 * This gets called from the edge IRQ handler to ACK the edge IRQ
268 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
277 raw_spin_lock(&pl061->lock); in pl061_irq_ack()
278 writeb(mask, pl061->base + GPIOIC); in pl061_irq_ack()
279 raw_spin_unlock(&pl061->lock); in pl061_irq_ack()
287 return irq_set_irq_wake(pl061->parent_irq, state); in pl061_irq_set_wake()
294 seq_printf(p, dev_name(gc->parent)); in pl061_irq_print_chip()
310 struct device *dev = &adev->dev; in pl061_probe()
317 return -ENOMEM; in pl061_probe()
319 pl061->base = devm_ioremap_resource(dev, &adev->res); in pl061_probe()
320 if (IS_ERR(pl061->base)) in pl061_probe()
321 return PTR_ERR(pl061->base); in pl061_probe()
323 raw_spin_lock_init(&pl061->lock); in pl061_probe()
324 pl061->gc.request = gpiochip_generic_request; in pl061_probe()
325 pl061->gc.free = gpiochip_generic_free; in pl061_probe()
326 pl061->gc.base = -1; in pl061_probe()
327 pl061->gc.get_direction = pl061_get_direction; in pl061_probe()
328 pl061->gc.direction_input = pl061_direction_input; in pl061_probe()
329 pl061->gc.direction_output = pl061_direction_output; in pl061_probe()
330 pl061->gc.get = pl061_get_value; in pl061_probe()
331 pl061->gc.set = pl061_set_value; in pl061_probe()
332 pl061->gc.ngpio = PL061_GPIO_NR; in pl061_probe()
333 pl061->gc.label = dev_name(dev); in pl061_probe()
334 pl061->gc.parent = dev; in pl061_probe()
335 pl061->gc.owner = THIS_MODULE; in pl061_probe()
340 writeb(0, pl061->base + GPIOIE); /* disable irqs */ in pl061_probe()
341 irq = adev->irq[0]; in pl061_probe()
343 dev_warn(&adev->dev, "IRQ support disabled\n"); in pl061_probe()
344 pl061->parent_irq = irq; in pl061_probe()
346 girq = &pl061->gc.irq; in pl061_probe()
348 girq->parent_handler = pl061_irq_handler; in pl061_probe()
349 girq->num_parents = 1; in pl061_probe()
350 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in pl061_probe()
352 if (!girq->parents) in pl061_probe()
353 return -ENOMEM; in pl061_probe()
354 girq->parents[0] = irq; in pl061_probe()
355 girq->default_type = IRQ_TYPE_NONE; in pl061_probe()
356 girq->handler = handle_bad_irq; in pl061_probe()
358 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); in pl061_probe()
372 int offset; in pl061_suspend() local
374 pl061->csave_regs.gpio_data = 0; in pl061_suspend()
375 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); in pl061_suspend()
376 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); in pl061_suspend()
377 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); in pl061_suspend()
378 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); in pl061_suspend()
379 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); in pl061_suspend()
381 for (offset = 0; offset < PL061_GPIO_NR; offset++) { in pl061_suspend()
382 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_suspend()
383 pl061->csave_regs.gpio_data |= in pl061_suspend()
384 pl061_get_value(&pl061->gc, offset) << offset; in pl061_suspend()
393 int offset; in pl061_resume() local
395 for (offset = 0; offset < PL061_GPIO_NR; offset++) { in pl061_resume()
396 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_resume()
397 pl061_direction_output(&pl061->gc, offset, in pl061_resume()
398 pl061->csave_regs.gpio_data & in pl061_resume()
399 (BIT(offset))); in pl061_resume()
401 pl061_direction_input(&pl061->gc, offset); in pl061_resume()
404 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); in pl061_resume()
405 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); in pl061_resume()
406 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); in pl061_resume()
407 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); in pl061_resume()