Lines Matching +full:nxp +full:- +full:i
1 // SPDX-License-Identifier: GPL-2.0-or-later
39 { .compatible = "nxp,pcf8574", (void *)8 },
40 { .compatible = "nxp,pcf8574a", (void *)8 },
41 { .compatible = "nxp,pca8574", (void *)8 },
42 { .compatible = "nxp,pca9670", (void *)8 },
43 { .compatible = "nxp,pca9672", (void *)8 },
44 { .compatible = "nxp,pca9674", (void *)8 },
45 { .compatible = "nxp,pcf8575", (void *)16 },
46 { .compatible = "nxp,pca8575", (void *)16 },
47 { .compatible = "nxp,pca9671", (void *)16 },
48 { .compatible = "nxp,pca9673", (void *)16 },
49 { .compatible = "nxp,pca9675", (void *)16 },
59 * that pin be used as an input; it's not an open-drain model, but acts
60 * a bit like one. This is described as "quasi-bidirectional"; read the
80 /*-------------------------------------------------------------------------*/
82 /* Talk to 8-bit I/O expander */
94 /* Talk to 16-bit I/O expander */
116 /*-------------------------------------------------------------------------*/
123 mutex_lock(&gpio->lock); in pcf857x_input()
124 gpio->out |= (1 << offset); in pcf857x_input()
125 status = gpio->write(gpio->client, gpio->out); in pcf857x_input()
126 mutex_unlock(&gpio->lock); in pcf857x_input()
136 value = gpio->read(gpio->client); in pcf857x_get()
144 int value = gpio->read(gpio->client); in pcf857x_get_multiple()
161 mutex_lock(&gpio->lock); in pcf857x_output()
163 gpio->out |= bit; in pcf857x_output()
165 gpio->out &= ~bit; in pcf857x_output()
166 status = gpio->write(gpio->client, gpio->out); in pcf857x_output()
167 mutex_unlock(&gpio->lock); in pcf857x_output()
182 mutex_lock(&gpio->lock); in pcf857x_set_multiple()
183 gpio->out &= ~*mask; in pcf857x_set_multiple()
184 gpio->out |= *bits & *mask; in pcf857x_set_multiple()
185 gpio->write(gpio->client, gpio->out); in pcf857x_set_multiple()
186 mutex_unlock(&gpio->lock); in pcf857x_set_multiple()
189 /*-------------------------------------------------------------------------*/
194 unsigned long change, i, status; in pcf857x_irq() local
196 status = gpio->read(gpio->client); in pcf857x_irq()
202 mutex_lock(&gpio->lock); in pcf857x_irq()
203 change = (gpio->status ^ status) & gpio->irq_enabled; in pcf857x_irq()
204 gpio->status = status; in pcf857x_irq()
205 mutex_unlock(&gpio->lock); in pcf857x_irq()
207 for_each_set_bit(i, &change, gpio->chip.ngpio) in pcf857x_irq()
208 handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i)); in pcf857x_irq()
222 return irq_set_irq_wake(gpio->client->irq, on); in pcf857x_irq_set_wake()
230 gpiochip_enable_irq(&gpio->chip, hwirq); in pcf857x_irq_enable()
231 gpio->irq_enabled |= (1 << hwirq); in pcf857x_irq_enable()
239 gpio->irq_enabled &= ~(1 << hwirq); in pcf857x_irq_disable()
240 gpiochip_disable_irq(&gpio->chip, hwirq); in pcf857x_irq_disable()
247 mutex_lock(&gpio->lock); in pcf857x_irq_bus_lock()
254 mutex_unlock(&gpio->lock); in pcf857x_irq_bus_sync_unlock()
271 /*-------------------------------------------------------------------------*/
279 device_property_read_u32(&client->dev, "lines-initial-states", &n_latch); in pcf857x_probe()
282 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); in pcf857x_probe()
284 return -ENOMEM; in pcf857x_probe()
286 mutex_init(&gpio->lock); in pcf857x_probe()
288 gpio->chip.base = -1; in pcf857x_probe()
289 gpio->chip.can_sleep = true; in pcf857x_probe()
290 gpio->chip.parent = &client->dev; in pcf857x_probe()
291 gpio->chip.owner = THIS_MODULE; in pcf857x_probe()
292 gpio->chip.get = pcf857x_get; in pcf857x_probe()
293 gpio->chip.get_multiple = pcf857x_get_multiple; in pcf857x_probe()
294 gpio->chip.set = pcf857x_set; in pcf857x_probe()
295 gpio->chip.set_multiple = pcf857x_set_multiple; in pcf857x_probe()
296 gpio->chip.direction_input = pcf857x_input; in pcf857x_probe()
297 gpio->chip.direction_output = pcf857x_output; in pcf857x_probe()
298 gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client); in pcf857x_probe()
301 * these parts, notably for output. It has a low-resolution in pcf857x_probe()
311 if (gpio->chip.ngpio == 8) { in pcf857x_probe()
312 gpio->write = i2c_write_le8; in pcf857x_probe()
313 gpio->read = i2c_read_le8; in pcf857x_probe()
315 if (!i2c_check_functionality(client->adapter, in pcf857x_probe()
317 status = -EIO; in pcf857x_probe()
329 } else if (gpio->chip.ngpio == 16) { in pcf857x_probe()
330 gpio->write = i2c_write_le16; in pcf857x_probe()
331 gpio->read = i2c_read_le16; in pcf857x_probe()
333 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) in pcf857x_probe()
334 status = -EIO; in pcf857x_probe()
341 dev_dbg(&client->dev, "unsupported number of gpios\n"); in pcf857x_probe()
342 status = -EINVAL; in pcf857x_probe()
348 gpio->chip.label = client->name; in pcf857x_probe()
350 gpio->client = client; in pcf857x_probe()
353 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. in pcf857x_probe()
365 * our software copy of the "latch" then matches the chip's all-ones in pcf857x_probe()
368 gpio->out = ~n_latch; in pcf857x_probe()
369 gpio->status = gpio->read(gpio->client); in pcf857x_probe()
372 if (client->irq) { in pcf857x_probe()
375 status = devm_request_threaded_irq(&client->dev, client->irq, in pcf857x_probe()
378 dev_name(&client->dev), gpio); in pcf857x_probe()
382 girq = &gpio->chip.irq; in pcf857x_probe()
385 girq->parent_handler = NULL; in pcf857x_probe()
386 girq->num_parents = 0; in pcf857x_probe()
387 girq->parents = NULL; in pcf857x_probe()
388 girq->default_type = IRQ_TYPE_NONE; in pcf857x_probe()
389 girq->handler = handle_level_irq; in pcf857x_probe()
390 girq->threaded = true; in pcf857x_probe()
393 status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio); in pcf857x_probe()
397 dev_info(&client->dev, "probed\n"); in pcf857x_probe()
402 dev_dbg(&client->dev, "probe error %d for '%s'\n", status, in pcf857x_probe()
403 client->name); in pcf857x_probe()
412 /* Drive all the I/O lines high */ in pcf857x_shutdown()
413 gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1); in pcf857x_shutdown()