Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
59 return port->devid == IMX23_GPIO; in is_imx23_gpio()
67 u32 pin_mask = 1 << d->hwirq; in mxs_gpio_set_irq_type()
70 struct mxs_gpio_port *port = gc->private; in mxs_gpio_set_irq_type()
72 int edge; in mxs_gpio_set_irq_type() local
74 if (!(ct->type & type)) in mxs_gpio_set_irq_type()
76 return -EINVAL; in mxs_gpio_set_irq_type()
78 port->both_edges &= ~pin_mask; in mxs_gpio_set_irq_type()
81 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; in mxs_gpio_set_irq_type()
83 edge = GPIO_INT_FALL_EDGE; in mxs_gpio_set_irq_type()
85 edge = GPIO_INT_RISE_EDGE; in mxs_gpio_set_irq_type()
86 port->both_edges |= pin_mask; in mxs_gpio_set_irq_type()
89 edge = GPIO_INT_RISE_EDGE; in mxs_gpio_set_irq_type()
92 edge = GPIO_INT_FALL_EDGE; in mxs_gpio_set_irq_type()
95 edge = GPIO_INT_LOW_LEV; in mxs_gpio_set_irq_type()
98 edge = GPIO_INT_HIGH_LEV; in mxs_gpio_set_irq_type()
101 return -EINVAL; in mxs_gpio_set_irq_type()
104 /* set level or edge */ in mxs_gpio_set_irq_type()
105 pin_addr = port->base + PINCTRL_IRQLEV(port); in mxs_gpio_set_irq_type()
106 if (edge & GPIO_INT_LEV_MASK) { in mxs_gpio_set_irq_type()
108 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type()
111 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type()
115 pin_addr = port->base + PINCTRL_IRQPOL(port); in mxs_gpio_set_irq_type()
116 if (edge & GPIO_INT_POL_MASK) in mxs_gpio_set_irq_type()
121 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); in mxs_gpio_set_irq_type()
128 u32 bit, val, edge; in mxs_flip_edge() local
133 pin_addr = port->base + PINCTRL_IRQPOL(port); in mxs_flip_edge()
135 edge = val & bit; in mxs_flip_edge()
137 if (edge) in mxs_flip_edge()
149 desc->irq_data.chip->irq_ack(&desc->irq_data); in mxs_gpio_irq_handler()
151 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) & in mxs_gpio_irq_handler()
152 readl(port->base + PINCTRL_IRQEN(port)); in mxs_gpio_irq_handler()
155 int irqoffset = fls(irq_stat) - 1; in mxs_gpio_irq_handler()
156 if (port->both_edges & (1 << irqoffset)) in mxs_gpio_irq_handler()
159 generic_handle_domain_irq(port->domain, irqoffset); in mxs_gpio_irq_handler()
165 * Set interrupt number "irq" in the GPIO as a wake-up source.
167 * wake-up enabled. When system is suspended, only selected GPIO interrupts
168 * need to have wake-up enabled.
170 * @param enable enable as wake-up if equal to non-zero
176 struct mxs_gpio_port *port = gc->private; in mxs_gpio_set_wake_irq()
179 enable_irq_wake(port->irq); in mxs_gpio_set_wake_irq()
181 disable_irq_wake(port->irq); in mxs_gpio_set_wake_irq()
192 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base, in mxs_gpio_init_gc()
193 port->base, handle_level_irq); in mxs_gpio_init_gc()
195 return -ENOMEM; in mxs_gpio_init_gc()
197 gc->private = port; in mxs_gpio_init_gc()
199 ct = &gc->chip_types[0]; in mxs_gpio_init_gc()
200 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mxs_gpio_init_gc()
201 ct->chip.irq_ack = irq_gc_ack_set_bit; in mxs_gpio_init_gc()
202 ct->chip.irq_mask = irq_gc_mask_disable_reg; in mxs_gpio_init_gc()
203 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in mxs_gpio_init_gc()
204 ct->chip.irq_set_type = mxs_gpio_set_irq_type; in mxs_gpio_init_gc()
205 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq; in mxs_gpio_init_gc()
206 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; in mxs_gpio_init_gc()
207 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR; in mxs_gpio_init_gc()
208 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET; in mxs_gpio_init_gc()
209 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR; in mxs_gpio_init_gc()
211 ct = &gc->chip_types[1]; in mxs_gpio_init_gc()
212 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mxs_gpio_init_gc()
213 ct->chip.irq_ack = irq_gc_ack_set_bit; in mxs_gpio_init_gc()
214 ct->chip.irq_mask = irq_gc_mask_disable_reg; in mxs_gpio_init_gc()
215 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in mxs_gpio_init_gc()
216 ct->chip.irq_set_type = mxs_gpio_set_irq_type; in mxs_gpio_init_gc()
217 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq; in mxs_gpio_init_gc()
218 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; in mxs_gpio_init_gc()
219 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR; in mxs_gpio_init_gc()
220 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET; in mxs_gpio_init_gc()
221 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR; in mxs_gpio_init_gc()
222 ct->handler = handle_level_irq; in mxs_gpio_init_gc()
224 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), in mxs_gpio_init_gc()
231 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) in mxs_gpio_to_irq() argument
235 return irq_find_mapping(port->domain, offset); in mxs_gpio_to_irq()
238 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) in mxs_gpio_get_direction() argument
241 u32 mask = 1 << offset; in mxs_gpio_get_direction()
244 dir = readl(port->base + PINCTRL_DOE(port)); in mxs_gpio_get_direction()
252 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
253 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
260 struct device_node *np = pdev->dev.of_node; in mxs_gpio_probe()
267 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); in mxs_gpio_probe()
269 return -ENOMEM; in mxs_gpio_probe()
271 port->id = of_alias_get_id(np, "gpio"); in mxs_gpio_probe()
272 if (port->id < 0) in mxs_gpio_probe()
273 return port->id; in mxs_gpio_probe()
274 port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev); in mxs_gpio_probe()
275 port->dev = &pdev->dev; in mxs_gpio_probe()
276 port->irq = platform_get_irq(pdev, 0); in mxs_gpio_probe()
277 if (port->irq < 0) in mxs_gpio_probe()
278 return port->irq; in mxs_gpio_probe()
289 return -EADDRNOTAVAIL; in mxs_gpio_probe()
291 port->base = base; in mxs_gpio_probe()
294 writel(0, port->base + PINCTRL_PIN2IRQ(port)); in mxs_gpio_probe()
295 writel(0, port->base + PINCTRL_IRQEN(port)); in mxs_gpio_probe()
298 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); in mxs_gpio_probe()
300 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); in mxs_gpio_probe()
306 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, in mxs_gpio_probe()
308 if (!port->domain) { in mxs_gpio_probe()
309 err = -ENODEV; in mxs_gpio_probe()
313 /* gpio-mxs can be a generic irq chip */ in mxs_gpio_probe()
319 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler, in mxs_gpio_probe()
322 err = bgpio_init(&port->gc, &pdev->dev, 4, in mxs_gpio_probe()
323 port->base + PINCTRL_DIN(port), in mxs_gpio_probe()
324 port->base + PINCTRL_DOUT(port) + MXS_SET, in mxs_gpio_probe()
325 port->base + PINCTRL_DOUT(port) + MXS_CLR, in mxs_gpio_probe()
326 port->base + PINCTRL_DOE(port), NULL, 0); in mxs_gpio_probe()
330 port->gc.to_irq = mxs_gpio_to_irq; in mxs_gpio_probe()
331 port->gc.get_direction = mxs_gpio_get_direction; in mxs_gpio_probe()
332 port->gc.base = port->id * 32; in mxs_gpio_probe()
334 err = gpiochip_add_data(&port->gc, port); in mxs_gpio_probe()
341 irq_domain_remove(port->domain); in mxs_gpio_probe()
343 iounmap(port->base); in mxs_gpio_probe()
349 .name = "gpio-mxs",